Philip Reames 4d629f9744

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226) ...

In review of bbde6b, I had originally proposed that we support the
legacy text format. As review evolved, it bacame clear this had been a
bad idea (too much complexity), but in order to let that patch finally
move forward, I approved the change with the variant. This change undoes
the variant, and updates all the tests to just use the array form.

2025-08-12 11:23:05 -07:00

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avoid-single-entry-value-location.mir

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backup-entry-values-usage.mir

[test] Remove redundant -march=x86-64 when target triple is specified in IR

2024-12-15 11:30:14 -08:00

bit-piece-dh.mir

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call-site-gnu-vs-dwarf5-attrs.mir

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call-site-param-mov16.mir

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callsite-stack-value.mir

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clobbered-fragments.mir

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complex-entryvalue.mir

[test] Remove redundant -march=x86-64 when target triple is specified in IR

2024-12-15 11:30:14 -08:00

dbg-call-site-spilled-arg-multiple-defs.mir

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dbg-call-site-spilled-arg.mir

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)

2025-08-12 11:23:05 -07:00

dbg-prologue-backup-loc2.mir

[DebugInfo] Handle trailing empty blocks when seeking prologue_end spot (#117320)

2024-11-26 14:24:25 +00:00

dbg-stack-value-range.mir

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dbgcall-site-clobbered-regs.mir

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dbgcall-site-copy-super-sub.mir

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dbgcall-site-interpretation.mir

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dbgcall-site-lea-interpretation.mir

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dbgcall-site-partial-describe-subreg.mir

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dbgcall-site-partial-describe.mir

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dbgcall-site-reference.mir

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dbgcall-site-reg-shuffle.mir

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dbgcall-site-two-fwd-reg-defs.mir

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dbginfo-entryvals.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

debug-call-site-param.mir

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debug-entry-value-operation.mir

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debug-loc-0.mir

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)

2025-08-12 11:23:05 -07:00

dvl-livedebugvalues-clobber.mir

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dvl-livedebugvalues-join.mir

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dvl-livedebugvalues-movements.mir

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dvl-livedebugvalues-spillrestore.mir

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dvl-livedebugvars-movements.mir

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dvl-livedebugvars-stackptr.mir

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empty-inline.mir

Reapply ccddb6ffad1, "Emit a worst-case prologue_end"

2024-11-14 10:30:17 +00:00

entry_value_clobbered_stack_copy.mir

[InstrRef] Skip clobbered EntryValue register recovery (#142478)

2025-06-27 10:30:29 -07:00

entry_value_gets_propagated_X86.mir

[InstrRef] Skip clobbered EntryValue register recovery (#142478)

2025-06-27 10:30:29 -07:00

entry-value-of-modified-param2.mir

[test] Remove redundant -march=x86-64 when target triple is specified in IR

2024-12-15 11:30:14 -08:00

entry-value-of-modified-param.mir

[test] Remove redundant -march=x86-64 when target triple is specified in IR

2024-12-15 11:30:14 -08:00

entry-values-diamond-bbs.mir

[test] Remove redundant -march=x86-64 when target triple is specified in IR

2024-12-15 11:30:14 -08:00

instr-ref-join-def-vphi.mir

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)

2025-08-12 11:23:05 -07:00

kill-after-spill.mir

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)

2025-08-12 11:23:05 -07:00

kill-entry-value-after-diamond-bbs2.mir

[test] Remove redundant -march=x86-64 when target triple is specified in IR

2024-12-15 11:30:14 -08:00

kill-entry-value-after-diamond-bbs.mir

[test] Remove redundant -march=x86-64 when target triple is specified in IR

2024-12-15 11:30:14 -08:00

ldv_unreachable_blocks2.mir

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ldv_unreachable_blocks.mir

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lit.local.cfg

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live-debug-values-3preds.mir

[test] Remove redundant -march=x86-64 when target triple is specified in IR

2024-12-15 11:30:14 -08:00

live-debug-values-bad-transfer2.mir

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live-debug-values-bad-transfer.mir

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live-debug-values-cutoffs.mir

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live-debug-values-entry-transfer.mir

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live-debug-values-fragments.mir

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live-debug-values-reg-copy.mir

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)

2025-08-12 11:23:05 -07:00

live-debug-values-restore-collide.mir

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live-debug-values-restore.mir

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)

2025-08-12 11:23:05 -07:00

live-debug-values-spill.mir

[test] Remove redundant -march=x86-64 when target triple is specified in IR

2024-12-15 11:30:14 -08:00

live-debug-values-stack-clobber.mir

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live-debug-values.mir

[test] Remove redundant -march=x86-64 when target triple is specified in IR

2024-12-15 11:30:14 -08:00

live-debug-vars-unused-arg-debugonly.mir

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)

2025-08-12 11:23:05 -07:00

live-debug-vars-unused-arg.mir

[MIR] Remove std::variant from multiple save/restore point handling [nfc] (#153226)

2025-08-12 11:23:05 -07:00

livedebugvalues_basic_diamond_match_clobber.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_basic_diamond_match_move.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_basic_diamond_one_clobber.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_basic_diamond_one_move.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_basic_diamond.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_basic_loop.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_bb_to_bb_clobbered.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_bb_to_bb_move_to_clobber.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_bb_to_bb.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_load_in_loop.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_loop_break_clobbered.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_loop_break.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_loop_clobbered.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_loop_diamond_clobber.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_loop_diamond_move.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_loop_diamond.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_loop_early_clobber.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_loop_terminated.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_loop_two_backedge_clobbered.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_loop_two_backedge.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_loop_within_loop_clobbered.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_loop_within_loop_moved.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_loop_within_loop_outer_moved.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_loop_within_loop.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues_many_loop_heads.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues-ignores-metaInstructions.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

livedebugvalues-limit.mir

[test] Remove redundant -march=x86-64 when target triple is specified in IR

2024-12-15 11:30:14 -08:00

livedebugvars-crossbb-interval.mir

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machine-cse.mir

Remove br i1 undef from some regression tests [NFC] (#115130)

2024-11-07 08:11:15 +00:00

machinesink-subreg.mir

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machinesink.mir

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merge-inline-loc1.mir

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merge-inline-loc2.mir

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merge-inline-loc3.mir

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merge-inline-loc4.mir

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mlicm-hoist-post-regalloc.mir

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mlicm-hoist-pre-regalloc.mir

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multiple-param-dbg-value-entry.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

no-cfi-loc.mir

[MIR,test] Change llc -march=x86-64 to -mtriple=x86_64

2024-12-15 11:23:08 -08:00

piece-entryval.mir

[test] Remove redundant -march=x86-64 when target triple is specified in IR

2024-12-15 11:30:14 -08:00

postra-subreg-sink.mir

[CodeGen][NewPM] Port "PostRAMachineSink" pass to NPM (#129690)

2025-07-10 13:10:46 +05:30

prolog-epilog-indirection.mir

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propagate-entry-value-cross-bbs.mir

[test] Remove redundant -march=x86-64 when target triple is specified in IR

2024-12-15 11:30:14 -08:00

regcoalescer.mir

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regcoalescing-clears-dead-dbgvals.mir

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remove-entry-value-from-loop.mir

[test] Remove redundant -march=x86-64 when target triple is specified in IR

2024-12-15 11:30:14 -08:00

remove-redundant-dbg-vals.mir

[CodeGen][NewPM] Port "RemoveRedundantDebugValues" to NPM (#129005)

2025-03-03 19:57:50 +07:00

sink-leaves-undef.mir

[CodeGen][NewPM] Port MachineSink to NPM (#115434)

2025-03-03 15:49:37 +05:30

unreachable-block-call-site.mir

[CodeGen][NPM] Port UnreachableMachineBlockElim to NPM (#136127)

2025-04-18 15:06:30 +05:30