80b08d1bb8
This patch adds support for describing per-write resource cycle counts
for ReadAdvance records via a new optional field called `tunables`.
This makes it possible to declare ReadAdvance records such as:
def : ReadAdvance<Read_C, 1, [Write_A, Write_B], [2]>;
The above will effectively declare two entries in the ReadAdvance
table for Read_C, one for Write_A with a cycle count of 1+2, and one for
Write_B with a cycle count of 1+0 (omitted values are assumed 0).
The field `tunables` provides a list of deltas relative to the base
`cycle` count of the ReadAdvance. Since the field is optional and
defaults to a list of 0's, this change doesn't affect current targets.
49 lines
1.4 KiB
TableGen
49 lines
1.4 KiB
TableGen
// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
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// RUN: not llvm-tblgen -gen-subtarget -I %p/../../include -DERROR1 %s 2>&1 | FileCheck --check-prefix=ERROR1 %s
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// Make sure that ReadAdvance entries with multiple writes are correctly
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// handled.
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include "llvm/Target/Target.td"
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def MyTarget : Target;
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let OutOperandList = (outs), InOperandList = (ins) in {
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def Inst_A : Instruction;
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def Inst_B : Instruction;
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def Inst_C : Instruction;
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}
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let CompleteModel = 0 in {
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def SchedModel_A: SchedMachineModel;
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}
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def Read_D : SchedRead;
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def Read_E : SchedRead;
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// CHECK: extern const llvm::MCReadAdvanceEntry MyTargetReadAdvanceTable[] = {
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// CHECK-NEXT: {0, 0, 0}, // Invalid
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// CHECK-NEXT: {0, 1, 1}, // #1
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// CHECK-NEXT: {0, 2, 3}, // #2
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// CHECK-NEXT: {0, 3, 2} // #3
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// CHECK-NEXT: }; // MyTargetReadAdvanceTable
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let SchedModel = SchedModel_A in {
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def Write_A : SchedWriteRes<[]>;
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def Write_B : SchedWriteRes<[]>;
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def Write_C : SchedWriteRes<[]>;
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def : InstRW<[Write_A], (instrs Inst_A)>;
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def : InstRW<[Write_B], (instrs Inst_B)>;
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def : InstRW<[Write_C, Read_D], (instrs Inst_C)>;
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def : ReadAdvance<Read_D, 2, [Write_A, Write_B, Write_C], [-1, 1]>;
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#ifdef ERROR1
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// ERROR1: error: assertion failed: cannot have more `tunables' than `writes'
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def : ReadAdvance<Read_E, 2, [Write_A, Write_B, Write_C], [1, 2, 3, 4]>;
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#endif
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}
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def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>;
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