9692dff7b7
Most of the processing in emitAction is in an unneeded else-block-- reduce indentation by exiting after the recursive call. `XXXGenCallingConv.inc` are identical before and after this patch for all targets.
79 lines
2.7 KiB
TableGen
79 lines
2.7 KiB
TableGen
// RUN: llvm-tblgen -gen-callingconv -I %p/../../include -I %p/Common %s | FileCheck %s
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// RUN: not llvm-tblgen -gen-callingconv -DERROR1 -I %p/../../include -I %p/Common %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR1 %s
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// RUN: not llvm-tblgen -gen-callingconv -DERROR2 -I %p/../../include -I %p/Common %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR2 %s
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include "reg-with-subregs-common.td"
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def CC_ABI1 : CallingConv<[
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// Use singleton definitions directly.
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CCIfType<[i32, f32],
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CCAssignToReg<[R8, R9, R10, R11, R12, R13, R14, R15]>>,
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// Use tuple definitions indirectly as strings.
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CCIfType<[i64, f64],
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CCAssignToRegTuple<["R8_R9", "R10_R11", "R12_R13", "R14_R15"]>>,
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CCIfType<[i128],
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CCAssignToRegTuple<["R8_R9_R10_R11", "R12_R13_R14_R15"]>>,
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CCIfType<[v8i32],
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CCAssignToRegTuple<["R8_R9_R10_R11_R12_R13_R14_R15"]>>,
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]>;
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// CHECK: if (LocVT == MVT::i32 ||
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// CHECK: LocVT == MVT::f32) {
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// CHECK: static const MCPhysReg RegList1[] = {
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// CHECK: R8, R9, R10, R11, R12, R13, R14, R15
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// CHECK: };
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// CHECK: if (MCRegister Reg = State.AllocateReg(RegList1)) {
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// CHECK: State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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// CHECK: return false;
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// CHECK: }
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// CHECK: }
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// CHECK: if (LocVT == MVT::i64 ||
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// CHECK: LocVT == MVT::f64) {
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// CHECK: static const MCPhysReg RegList2[] = {
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// CHECK: R8_R9, R10_R11, R12_R13, R14_R15
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// CHECK: };
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// CHECK: if (MCRegister Reg = State.AllocateReg(RegList2)) {
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// CHECK: State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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// CHECK: return false;
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// CHECK: }
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// CHECK: }
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// CHECK: if (LocVT == MVT::i128) {
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// CHECK: static const MCPhysReg RegList3[] = {
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// CHECK: R8_R9_R10_R11, R12_R13_R14_R15
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// CHECK: };
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// CHECK: if (MCRegister Reg = State.AllocateReg(RegList3)) {
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// CHECK: State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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// CHECK: return false;
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// CHECK: }
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// CHECK: }
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// CHECK: if (LocVT == MVT::v8i32) {
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// CHECK: if (MCRegister Reg = State.AllocateReg(R8_R9_R10_R11_R12_R13_R14_R15)) {
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// CHECK: State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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// CHECK: return false;
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// CHECK: }
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// CHECK: }
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#ifdef ERROR1
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def CC_ABI2 : CallingConv<[
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// Test that referencing an undefined tuple is diagnosed as an error.
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// CHECK-ERROR1: error: register not defined: "R89_R33"
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CCIfType<[i64, f64],
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CCAssignToRegTuple<["R89_R33", "R12_R13", "R14_R15"]>>,
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]>;
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#endif
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#ifdef ERROR2
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def CC_ABI3 : CallingConv<[
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// Currently an error: Use tuple definitions directly.
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// CHECK-ERROR2: error: Variable not defined: 'R8_R9_R10_R11'
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CCIfType<[i128],
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CCAssignToRegTuple<[R8_R9_R10_R11, R12_R13_R14_R15]>>,
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]>;
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#endif
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