e40cabfea4
Problem description: https://github.com/llvm/llvm-project/pull/81008#issuecomment-1933468520 Solution: https://github.com/llvm/llvm-project/pull/81008#issuecomment-1934192548 (choose plan2)
388 lines
15 KiB
LLVM
388 lines
15 KiB
LLVM
;; Test to make sure that function's definiton and summary matches.
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; RUN: split-file %s %t
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; RUN: opt -thinlto-bc %t/main.ll >%t/main.o
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; RUN: opt -thinlto-bc %t/b.ll >%t/b.o
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; RUN: opt -thinlto-bc %t/c.ll >%t/c.o
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; RUN: llvm-lto2 run %t/b.o %t/c.o %t/main.o -enable-memprof-context-disambiguation \
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; RUN: -supports-hot-cold-new -o %t/a.out \
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; RUN: -r=%t/main.o,main,plx \
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; RUN: -r=%t/b.o,_Z1bv,plx \
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; RUN: -r=%t/b.o,_Z3fooIiET_S0_S0_,plx \
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; RUN: -r=%t/b.o,_Znwm \
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; RUN: -r=%t/c.o,_Z1cv,plx \
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; RUN: -r=%t/c.o,_Z3fooIiET_S0_S0_ \
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; RUN: -r=%t/c.o,_Z3barIiET_S0_S0_,plx \
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; RUN: -r=%t/c.o,_Znwm \
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; RUN: -r=%t/main.o,_Z1bv \
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; RUN: -r=%t/main.o,_Z1cv \
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; RUN: -r=%t/main.o,_Z3fooIiET_S0_S0_
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;; foo has two copys:
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;; foo in b.ll is prevailing and inlines bar.
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;; foo in c.ll isn't prevailing and doesn't inline bar.
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;; main will import foo in c.ll and foo's summary in b.ll default.
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;--- main.ll
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; ModuleID = 'main.cc'
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source_filename = "main.cc"
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; Function Attrs: mustprogress norecurse uwtable
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define dso_local noundef i32 @main() #0 {
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entry:
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%retval = alloca i32, align 4
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store i32 0, ptr %retval, align 4
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%call = call noundef i32 @_Z1bv(), !callsite !6
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%call1 = call noundef i32 @_Z1cv(), !callsite !7
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%add = add nsw i32 %call, %call1
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%call2 = call noundef i32 @_Z3fooIiET_S0_S0_(i32 noundef 1, i32 noundef 2), !callsite !8
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%add3 = add nsw i32 %add, %call2
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ret i32 %add3
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}
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declare noundef i32 @_Z1bv() #1
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declare noundef i32 @_Z1cv() #1
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declare noundef i32 @_Z3fooIiET_S0_S0_(i32 noundef, i32 noundef) #1
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attributes #0 = { mustprogress norecurse uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
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attributes #1 = { "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
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!llvm.module.flags = !{!0, !1, !2, !3, !4}
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!llvm.ident = !{!5}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 8, !"PIC Level", i32 2}
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!2 = !{i32 7, !"PIE Level", i32 2}
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!3 = !{i32 7, !"uwtable", i32 2}
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!4 = !{i32 7, !"frame-pointer", i32 2}
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!5 = !{!"clang version 19.0.0"}
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!6 = !{i64 1}
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!7 = !{i64 5}
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!8 = !{i64 7}
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;--- c.ll
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; ModuleID = 'c.cc'
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source_filename = "c.cc"
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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$_Z3fooIiET_S0_S0_ = comdat any
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$_Z3barIiET_S0_S0_ = comdat any
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; Function Attrs: mustprogress noinline optnone uwtable
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define dso_local noundef i32 @_Z1cv() #0 {
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entry:
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%num1 = alloca i32, align 4
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%num2 = alloca i32, align 4
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store i32 1, ptr %num1, align 4
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store i32 1, ptr %num2, align 4
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%0 = load i32, ptr %num1, align 4
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%1 = load i32, ptr %num2, align 4
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%call = call noundef i32 @_Z3fooIiET_S0_S0_(i32 noundef %0, i32 noundef %1), !callsite !6
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ret i32 %call
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}
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; Function Attrs: mustprogress uwtable
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define linkonce_odr dso_local noundef i32 @_Z3fooIiET_S0_S0_(i32 noundef %a, i32 noundef %b) #3 comdat {
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entry:
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%a.addr = alloca i32, align 4
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%b.addr = alloca i32, align 4
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%rtn = alloca i32, align 4
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store i32 %a, ptr %a.addr, align 4
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store i32 %b, ptr %b.addr, align 4
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%0 = load i32, ptr %a.addr, align 4
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%1 = load i32, ptr %b.addr, align 4
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%call = call noundef i32 @_Z3barIiET_S0_S0_(i32 noundef %0, i32 noundef %1), !callsite !7
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store i32 %call, ptr %rtn, align 4
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%2 = load i32, ptr %rtn, align 4
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ret i32 %2
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}
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; Function Attrs: mustprogress noinline optnone uwtable
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define linkonce_odr dso_local noundef i32 @_Z3barIiET_S0_S0_(i32 noundef %a, i32 noundef %b) #0 comdat {
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entry:
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%a.addr = alloca i32, align 4
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%b.addr = alloca i32, align 4
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%c = alloca ptr, align 8
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%d = alloca ptr, align 8
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store i32 %a, ptr %a.addr, align 4
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store i32 %b, ptr %b.addr, align 4
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%0 = load i32, ptr %a.addr, align 4
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%add = add nsw i32 %0, 1
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store i32 %add, ptr %a.addr, align 4
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%1 = load i32, ptr %b.addr, align 4
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%add1 = add nsw i32 %1, 1
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store i32 %add1, ptr %b.addr, align 4
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%2 = load i32, ptr %a.addr, align 4
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%add2 = add nsw i32 %2, 1
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store i32 %add2, ptr %a.addr, align 4
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%3 = load i32, ptr %b.addr, align 4
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%add3 = add nsw i32 %3, 1
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store i32 %add3, ptr %b.addr, align 4
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%4 = load i32, ptr %a.addr, align 4
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%add4 = add nsw i32 %4, 1
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store i32 %add4, ptr %a.addr, align 4
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%5 = load i32, ptr %b.addr, align 4
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%add5 = add nsw i32 %5, 1
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store i32 %add5, ptr %b.addr, align 4
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%6 = load i32, ptr %a.addr, align 4
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%add6 = add nsw i32 %6, 1
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store i32 %add6, ptr %a.addr, align 4
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%7 = load i32, ptr %b.addr, align 4
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%add7 = add nsw i32 %7, 1
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store i32 %add7, ptr %b.addr, align 4
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%8 = load i32, ptr %a.addr, align 4
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%add8 = add nsw i32 %8, 1
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store i32 %add8, ptr %a.addr, align 4
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%9 = load i32, ptr %b.addr, align 4
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%add9 = add nsw i32 %9, 1
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store i32 %add9, ptr %b.addr, align 4
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%10 = load i32, ptr %a.addr, align 4
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%add10 = add nsw i32 %10, 1
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store i32 %add10, ptr %a.addr, align 4
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%11 = load i32, ptr %b.addr, align 4
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%add11 = add nsw i32 %11, 1
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store i32 %add11, ptr %b.addr, align 4
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%12 = load i32, ptr %a.addr, align 4
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%add12 = add nsw i32 %12, 1
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store i32 %add12, ptr %a.addr, align 4
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%13 = load i32, ptr %b.addr, align 4
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%add13 = add nsw i32 %13, 1
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store i32 %add13, ptr %b.addr, align 4
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%14 = load i32, ptr %a.addr, align 4
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%add14 = add nsw i32 %14, 1
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store i32 %add14, ptr %a.addr, align 4
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%15 = load i32, ptr %b.addr, align 4
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%add15 = add nsw i32 %15, 1
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store i32 %add15, ptr %b.addr, align 4
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%16 = load i32, ptr %a.addr, align 4
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%add16 = add nsw i32 %16, 1
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store i32 %add16, ptr %a.addr, align 4
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%17 = load i32, ptr %b.addr, align 4
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%add17 = add nsw i32 %17, 1
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store i32 %add17, ptr %b.addr, align 4
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%18 = load i32, ptr %a.addr, align 4
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%add18 = add nsw i32 %18, 1
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store i32 %add18, ptr %a.addr, align 4
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%19 = load i32, ptr %b.addr, align 4
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%add19 = add nsw i32 %19, 1
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store i32 %add19, ptr %b.addr, align 4
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%20 = load i32, ptr %a.addr, align 4
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%add20 = add nsw i32 %20, 1
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store i32 %add20, ptr %a.addr, align 4
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%21 = load i32, ptr %b.addr, align 4
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%add21 = add nsw i32 %21, 1
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store i32 %add21, ptr %b.addr, align 4
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%22 = load i32, ptr %a.addr, align 4
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%add22 = add nsw i32 %22, 1
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store i32 %add22, ptr %a.addr, align 4
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%23 = load i32, ptr %b.addr, align 4
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%add23 = add nsw i32 %23, 1
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store i32 %add23, ptr %b.addr, align 4
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%call = call noalias noundef nonnull ptr @_Znwm(i64 noundef 4) #2, !callsite !8
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store i32 1, ptr %call, align 4
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store ptr %call, ptr %c, align 8
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%call24 = call noalias noundef nonnull ptr @_Znwm(i64 noundef 4) #2, !callsite !9
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store i32 1, ptr %call24, align 4
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store ptr %call24, ptr %d, align 8
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%24 = load i32, ptr %a.addr, align 4
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%25 = load i32, ptr %b.addr, align 4
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%cmp = icmp sgt i32 %24, %25
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br i1 %cmp, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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%26 = load i32, ptr %a.addr, align 4
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br label %cond.end
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cond.false: ; preds = %entry
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%27 = load i32, ptr %b.addr, align 4
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi i32 [ %26, %cond.true ], [ %27, %cond.false ]
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ret i32 %cond
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}
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; Function Attrs: nobuiltin allocsize(0)
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declare noundef nonnull ptr @_Znwm(i64 noundef) #1
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attributes #0 = { mustprogress noinline optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
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attributes #1 = { nobuiltin allocsize(0) "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
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attributes #2 = { builtin allocsize(0) }
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attributes #3 = { mustprogress uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
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!llvm.module.flags = !{!0, !1, !2, !3, !4}
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!llvm.ident = !{!5}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 8, !"PIC Level", i32 2}
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!2 = !{i32 7, !"PIE Level", i32 2}
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!3 = !{i32 7, !"uwtable", i32 2}
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!4 = !{i32 7, !"frame-pointer", i32 2}
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!5 = !{!"clang version 19.0.0"}
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!6 = !{i64 6}
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!7 = !{i64 3}
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!8 = !{i64 4}
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!9 = !{i64 9}
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;--- b.ll
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; ModuleID = 'b.cc'
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source_filename = "b.cc"
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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$_Z3fooIiET_S0_S0_ = comdat any
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; Function Attrs: mustprogress noinline optnone uwtable
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define dso_local noundef i32 @_Z1bv() #0 {
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entry:
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%num1 = alloca i32, align 4
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%num2 = alloca i32, align 4
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store i32 0, ptr %num1, align 4
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store i32 0, ptr %num2, align 4
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%0 = load i32, ptr %num1, align 4
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%1 = load i32, ptr %num2, align 4
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%call = call noundef i32 @_Z3fooIiET_S0_S0_(i32 noundef %0, i32 noundef %1), !callsite !6
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ret i32 %call
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}
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; Function Attrs: mustprogress uwtable
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define linkonce_odr dso_local noundef i32 @_Z3fooIiET_S0_S0_(i32 noundef %a, i32 noundef %b) #3 comdat {
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entry:
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%a.addr.i = alloca i32, align 4
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%b.addr.i = alloca i32, align 4
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%c.i = alloca ptr, align 8
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%d.i = alloca ptr, align 8
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%a.addr = alloca i32, align 4
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%b.addr = alloca i32, align 4
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%rtn = alloca i32, align 4
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store i32 %a, ptr %a.addr, align 4
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store i32 %b, ptr %b.addr, align 4
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%0 = load i32, ptr %a.addr, align 4
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%1 = load i32, ptr %b.addr, align 4
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store i32 %0, ptr %a.addr.i, align 4
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store i32 %1, ptr %b.addr.i, align 4
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%2 = load i32, ptr %a.addr.i, align 4
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%add.i = add nsw i32 %2, 1
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store i32 %add.i, ptr %a.addr.i, align 4
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%3 = load i32, ptr %b.addr.i, align 4
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%add1.i = add nsw i32 %3, 1
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store i32 %add1.i, ptr %b.addr.i, align 4
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%4 = load i32, ptr %a.addr.i, align 4
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%add2.i = add nsw i32 %4, 1
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store i32 %add2.i, ptr %a.addr.i, align 4
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%5 = load i32, ptr %b.addr.i, align 4
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%add3.i = add nsw i32 %5, 1
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store i32 %add3.i, ptr %b.addr.i, align 4
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%6 = load i32, ptr %a.addr.i, align 4
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%add4.i = add nsw i32 %6, 1
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store i32 %add4.i, ptr %a.addr.i, align 4
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%7 = load i32, ptr %b.addr.i, align 4
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%add5.i = add nsw i32 %7, 1
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store i32 %add5.i, ptr %b.addr.i, align 4
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%8 = load i32, ptr %a.addr.i, align 4
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%add6.i = add nsw i32 %8, 1
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store i32 %add6.i, ptr %a.addr.i, align 4
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%9 = load i32, ptr %b.addr.i, align 4
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%add7.i = add nsw i32 %9, 1
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store i32 %add7.i, ptr %b.addr.i, align 4
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%10 = load i32, ptr %a.addr.i, align 4
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%add8.i = add nsw i32 %10, 1
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store i32 %add8.i, ptr %a.addr.i, align 4
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%11 = load i32, ptr %b.addr.i, align 4
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%add9.i = add nsw i32 %11, 1
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store i32 %add9.i, ptr %b.addr.i, align 4
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%12 = load i32, ptr %a.addr.i, align 4
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%add10.i = add nsw i32 %12, 1
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store i32 %add10.i, ptr %a.addr.i, align 4
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%13 = load i32, ptr %b.addr.i, align 4
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%add11.i = add nsw i32 %13, 1
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store i32 %add11.i, ptr %b.addr.i, align 4
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%14 = load i32, ptr %a.addr.i, align 4
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%add12.i = add nsw i32 %14, 1
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store i32 %add12.i, ptr %a.addr.i, align 4
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%15 = load i32, ptr %b.addr.i, align 4
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%add13.i = add nsw i32 %15, 1
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store i32 %add13.i, ptr %b.addr.i, align 4
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%16 = load i32, ptr %a.addr.i, align 4
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%add14.i = add nsw i32 %16, 1
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store i32 %add14.i, ptr %a.addr.i, align 4
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%17 = load i32, ptr %b.addr.i, align 4
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%add15.i = add nsw i32 %17, 1
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store i32 %add15.i, ptr %b.addr.i, align 4
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%18 = load i32, ptr %a.addr.i, align 4
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%add16.i = add nsw i32 %18, 1
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store i32 %add16.i, ptr %a.addr.i, align 4
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%19 = load i32, ptr %b.addr.i, align 4
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%add17.i = add nsw i32 %19, 1
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store i32 %add17.i, ptr %b.addr.i, align 4
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%20 = load i32, ptr %a.addr.i, align 4
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%add18.i = add nsw i32 %20, 1
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store i32 %add18.i, ptr %a.addr.i, align 4
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%21 = load i32, ptr %b.addr.i, align 4
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%add19.i = add nsw i32 %21, 1
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store i32 %add19.i, ptr %b.addr.i, align 4
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%22 = load i32, ptr %a.addr.i, align 4
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%add20.i = add nsw i32 %22, 1
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store i32 %add20.i, ptr %a.addr.i, align 4
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%23 = load i32, ptr %b.addr.i, align 4
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%add21.i = add nsw i32 %23, 1
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store i32 %add21.i, ptr %b.addr.i, align 4
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%24 = load i32, ptr %a.addr.i, align 4
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%add22.i = add nsw i32 %24, 1
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store i32 %add22.i, ptr %a.addr.i, align 4
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%25 = load i32, ptr %b.addr.i, align 4
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%add23.i = add nsw i32 %25, 1
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store i32 %add23.i, ptr %b.addr.i, align 4
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%call.i = call noalias noundef nonnull ptr @_Znwm(i64 noundef 4) #2, !callsite !7
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store i32 1, ptr %call.i, align 4
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|
store ptr %call.i, ptr %c.i, align 8
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|
%call24.i = call noalias noundef nonnull ptr @_Znwm(i64 noundef 4) #2, !callsite !8
|
|
store i32 1, ptr %call24.i, align 4
|
|
store ptr %call24.i, ptr %d.i, align 8
|
|
%26 = load i32, ptr %a.addr.i, align 4
|
|
%27 = load i32, ptr %b.addr.i, align 4
|
|
%cmp.i = icmp sgt i32 %26, %27
|
|
br i1 %cmp.i, label %cond.true.i, label %cond.false.i
|
|
|
|
cond.true.i: ; preds = %entry
|
|
%28 = load i32, ptr %a.addr.i, align 4
|
|
br label %_Z3barIiET_S0_S0_.exit
|
|
|
|
cond.false.i: ; preds = %entry
|
|
%29 = load i32, ptr %b.addr.i, align 4
|
|
br label %_Z3barIiET_S0_S0_.exit
|
|
|
|
_Z3barIiET_S0_S0_.exit: ; preds = %cond.true.i, %cond.false.i
|
|
%cond.i = phi i32 [ %28, %cond.true.i ], [ %29, %cond.false.i ]
|
|
store i32 %cond.i, ptr %rtn, align 4
|
|
%30 = load i32, ptr %rtn, align 4
|
|
ret i32 %30
|
|
}
|
|
|
|
; Function Attrs: nobuiltin allocsize(0)
|
|
declare noundef nonnull ptr @_Znwm(i64 noundef) #1
|
|
|
|
attributes #0 = { mustprogress noinline optnone uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
|
|
attributes #1 = { nobuiltin allocsize(0) "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
|
|
attributes #2 = { builtin allocsize(0) }
|
|
attributes #3 = { mustprogress uwtable "frame-pointer"="all" "min-legal-vector-width"="0" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cmov,+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" }
|
|
|
|
!llvm.module.flags = !{!0, !1, !2, !3, !4}
|
|
!llvm.ident = !{!5}
|
|
|
|
!0 = !{i32 1, !"wchar_size", i32 4}
|
|
!1 = !{i32 8, !"PIC Level", i32 2}
|
|
!2 = !{i32 7, !"PIE Level", i32 2}
|
|
!3 = !{i32 7, !"uwtable", i32 2}
|
|
!4 = !{i32 7, !"frame-pointer", i32 2}
|
|
!5 = !{!"clang version 19.0.0"}
|
|
!6 = !{i64 2}
|
|
!7 = !{i64 4, i64 3}
|
|
!8 = !{i64 9, i64 3}
|