2320cddfc2
Enabling one of MemorySSA or MD implies the other is off. Already approved in https://github.com/llvm/llvm-project/pull/149473 but I had to revert as I missed updating one test.
114 lines
3.7 KiB
LLVM
114 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S -passes=gvn < %s | FileCheck --check-prefixes=CHECK,MDEP %s
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; RUN: opt -S -passes='gvn<memoryssa>' -verify-analysis-invalidation < %s | FileCheck --check-prefixes=CHECK,MSSA %s
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declare i32 @setjmp() returns_twice
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declare void @longjmp()
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declare ptr @malloc(i64)
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define i32 @test() {
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; CHECK-LABEL: define i32 @test() {
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; CHECK-NEXT: [[MALLOC:%.*]] = call noalias ptr @malloc(i64 4)
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; CHECK-NEXT: store i32 10, ptr [[MALLOC]], align 4
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; CHECK-NEXT: [[SJ:%.*]] = call i32 @setjmp()
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[SJ]], 0
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; CHECK-NEXT: br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
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; CHECK: [[IF_THEN]]:
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; CHECK-NEXT: store i32 20, ptr [[MALLOC]], align 4
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; CHECK-NEXT: call void @longjmp()
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; CHECK-NEXT: unreachable
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; CHECK: [[IF_END]]:
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; CHECK-NEXT: [[RES:%.*]] = load i32, ptr [[MALLOC]], align 4
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%malloc = call noalias ptr @malloc(i64 4)
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store i32 10, ptr %malloc, align 4
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%sj = call i32 @setjmp()
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%cmp = icmp eq i32 %sj, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store i32 20, ptr %malloc
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call void @longjmp()
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unreachable
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if.end:
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%res = load i32, ptr %malloc
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ret i32 %res
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}
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; We are still allowed to optimize non-volatile accesses to allocas.
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define i32 @test_alloca() {
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; MDEP-LABEL: define i32 @test_alloca() {
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; MDEP-NEXT: [[ALLOC:%.*]] = alloca i43, align 8
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; MDEP-NEXT: store i32 10, ptr [[ALLOC]], align 4
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; MDEP-NEXT: [[SJ:%.*]] = call i32 @setjmp()
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; MDEP-NEXT: [[CMP:%.*]] = icmp eq i32 [[SJ]], 0
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; MDEP-NEXT: br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
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; MDEP: [[IF_THEN]]:
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; MDEP-NEXT: store i32 20, ptr [[ALLOC]], align 4
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; MDEP-NEXT: call void @longjmp()
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; MDEP-NEXT: unreachable
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; MDEP: [[IF_END]]:
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; MDEP-NEXT: ret i32 10
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;
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; MSSA-LABEL: define i32 @test_alloca() {
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; MSSA-NEXT: [[ALLOC:%.*]] = alloca i43, align 8
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; MSSA-NEXT: store i32 10, ptr [[ALLOC]], align 4
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; MSSA-NEXT: [[SJ:%.*]] = call i32 @setjmp()
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; MSSA-NEXT: [[CMP:%.*]] = icmp eq i32 [[SJ]], 0
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; MSSA-NEXT: br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
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; MSSA: [[IF_THEN]]:
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; MSSA-NEXT: store i32 20, ptr [[ALLOC]], align 4
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; MSSA-NEXT: call void @longjmp()
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; MSSA-NEXT: unreachable
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; MSSA: [[IF_END]]:
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; MSSA-NEXT: [[RES:%.*]] = load i32, ptr [[ALLOC]], align 4
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; MSSA-NEXT: ret i32 [[RES]]
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;
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%alloc = alloca i43
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store i32 10, ptr %alloc, align 4
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%sj = call i32 @setjmp()
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%cmp = icmp eq i32 %sj, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store i32 20, ptr %alloc
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call void @longjmp()
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unreachable
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if.end:
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%res = load i32, ptr %alloc
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ret i32 %res
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}
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define i32 @test_alloca_volatile() {
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; CHECK-LABEL: define i32 @test_alloca_volatile() {
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; CHECK-NEXT: [[ALLOC:%.*]] = alloca i43, align 8
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; CHECK-NEXT: store volatile i32 10, ptr [[ALLOC]], align 4
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; CHECK-NEXT: [[SJ:%.*]] = call i32 @setjmp()
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[SJ]], 0
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; CHECK-NEXT: br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
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; CHECK: [[IF_THEN]]:
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; CHECK-NEXT: store volatile i32 20, ptr [[ALLOC]], align 4
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; CHECK-NEXT: call void @longjmp()
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; CHECK-NEXT: unreachable
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; CHECK: [[IF_END]]:
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; CHECK-NEXT: [[RES:%.*]] = load volatile i32, ptr [[ALLOC]], align 4
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%alloc = alloca i43
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store volatile i32 10, ptr %alloc, align 4
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%sj = call i32 @setjmp()
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%cmp = icmp eq i32 %sj, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store volatile i32 20, ptr %alloc
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call void @longjmp()
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unreachable
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if.end:
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%res = load volatile i32, ptr %alloc
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ret i32 %res
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}
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