29441e4f5f
This PR removes the old `nocapture` attribute, replacing it with the new `captures` attribute introduced in #116990. This change is intended to be essentially NFC, replacing existing uses of `nocapture` with `captures(none)` without adding any new analysis capabilities. Making use of non-`none` values is left for a followup. Some notes: * `nocapture` will be upgraded to `captures(none)` by the bitcode reader. * `nocapture` will also be upgraded by the textual IR reader. This is to make it easier to use old IR files and somewhat reduce the test churn in this PR. * Helper APIs like `doesNotCapture()` will check for `captures(none)`. * MLIR import will convert `captures(none)` into an `llvm.nocapture` attribute. The representation in the LLVM IR dialect should be updated separately.
157 lines
6.3 KiB
LLVM
157 lines
6.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
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; RUN: opt < %s -passes=indvars -S | FileCheck %s
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;
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; PR1301
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; Do a bunch of analysis and prove that the loops can use an i32 trip
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; count without casting.
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;
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; Note that all four functions should actually be converted to
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; memset. However, this test case validates indvars behavior. We
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; don't check that phis are "folded together" because that is a job
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; for loop strength reduction. But indvars must remove sext, zext, and add i8.
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;
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; ModuleID = 'ada.bc'
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32"
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target triple = "i686-pc-linux-gnu"
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define void @kinds__sbytezero(ptr nocapture %a) nounwind {
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; CHECK-LABEL: define void @kinds__sbytezero(
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; CHECK-SAME: ptr captures(none) [[A:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: bb.thread:
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; CHECK-NEXT: [[TMP46:%.*]] = getelementptr [256 x i32], ptr [[A]], i32 0, i32 0
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; CHECK-NEXT: store i32 0, ptr [[TMP46]], align 4
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; CHECK-NEXT: br label [[BB:%.*]]
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; CHECK: bb:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ [[INDVARS_IV_NEXT:%.*]], [[BB]] ], [ -128, [[BB_THREAD:%.*]] ]
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i32 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[TMP3:%.*]] = add nsw i32 [[INDVARS_IV_NEXT]], 128
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr [256 x i32], ptr [[A]], i32 0, i32 [[TMP3]]
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; CHECK-NEXT: store i32 0, ptr [[TMP4]], align 4
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; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[INDVARS_IV_NEXT]], 127
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; CHECK-NEXT: br i1 [[TMP0]], label [[RETURN:%.*]], label [[BB]]
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; CHECK: return:
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; CHECK-NEXT: ret void
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;
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bb.thread:
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%tmp46 = getelementptr [256 x i32], ptr %a, i32 0, i32 0 ; <ptr> [#uses=1]
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store i32 0, ptr %tmp46
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br label %bb
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bb: ; preds = %bb, %bb.thread
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%i.0.reg2mem.0 = phi i8 [ -128, %bb.thread ], [ %tmp8, %bb ] ; <i8> [#uses=1]
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%tmp8 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=3]
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%tmp1 = sext i8 %tmp8 to i32 ; <i32> [#uses=1]
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%tmp3 = add i32 %tmp1, 128 ; <i32> [#uses=1]
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%tmp4 = getelementptr [256 x i32], ptr %a, i32 0, i32 %tmp3 ; <ptr> [#uses=1]
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store i32 0, ptr %tmp4
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%0 = icmp eq i8 %tmp8, 127 ; <i1> [#uses=1]
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br i1 %0, label %return, label %bb
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return: ; preds = %bb
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ret void
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}
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define void @kinds__ubytezero(ptr nocapture %a) nounwind {
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; CHECK-LABEL: define void @kinds__ubytezero(
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; CHECK-SAME: ptr captures(none) [[A:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: bb.thread:
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; CHECK-NEXT: [[TMP35:%.*]] = getelementptr [256 x i32], ptr [[A]], i32 0, i32 0
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; CHECK-NEXT: store i32 0, ptr [[TMP35]], align 4
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; CHECK-NEXT: br label [[BB:%.*]]
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; CHECK: bb:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ [[INDVARS_IV_NEXT:%.*]], [[BB]] ], [ 0, [[BB_THREAD:%.*]] ]
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i32 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr [256 x i32], ptr [[A]], i32 0, i32 [[INDVARS_IV_NEXT]]
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; CHECK-NEXT: store i32 0, ptr [[TMP3]], align 4
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; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[INDVARS_IV_NEXT]], 255
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; CHECK-NEXT: br i1 [[TMP0]], label [[RETURN:%.*]], label [[BB]]
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; CHECK: return:
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; CHECK-NEXT: ret void
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;
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bb.thread:
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%tmp35 = getelementptr [256 x i32], ptr %a, i32 0, i32 0 ; <ptr> [#uses=1]
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store i32 0, ptr %tmp35
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br label %bb
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bb: ; preds = %bb, %bb.thread
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%i.0.reg2mem.0 = phi i8 [ 0, %bb.thread ], [ %tmp7, %bb ] ; <i8> [#uses=1]
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%tmp7 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=3]
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%tmp1 = zext i8 %tmp7 to i32 ; <i32> [#uses=1]
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%tmp3 = getelementptr [256 x i32], ptr %a, i32 0, i32 %tmp1 ; <ptr> [#uses=1]
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store i32 0, ptr %tmp3
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%0 = icmp eq i8 %tmp7, -1 ; <i1> [#uses=1]
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br i1 %0, label %return, label %bb
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return: ; preds = %bb
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ret void
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}
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define void @kinds__srangezero(ptr nocapture %a) nounwind {
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; CHECK-LABEL: define void @kinds__srangezero(
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; CHECK-SAME: ptr captures(none) [[A:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: bb.thread:
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; CHECK-NEXT: br label [[BB:%.*]]
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; CHECK: bb:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ [[INDVARS_IV_NEXT:%.*]], [[BB]] ], [ -10, [[BB_THREAD:%.*]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = add nsw i32 [[INDVARS_IV]], 10
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr [21 x i32], ptr [[A]], i32 0, i32 [[TMP4]]
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; CHECK-NEXT: store i32 0, ptr [[TMP5]], align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i32 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INDVARS_IV_NEXT]], 11
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[RETURN:%.*]], label [[BB]]
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; CHECK: return:
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; CHECK-NEXT: ret void
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;
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bb.thread:
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br label %bb
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bb: ; preds = %bb, %bb.thread
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%i.0.reg2mem.0 = phi i8 [ -10, %bb.thread ], [ %tmp7, %bb ] ; <i8> [#uses=2]
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%tmp12 = sext i8 %i.0.reg2mem.0 to i32 ; <i32> [#uses=1]
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%tmp4 = add i32 %tmp12, 10 ; <i32> [#uses=1]
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%tmp5 = getelementptr [21 x i32], ptr %a, i32 0, i32 %tmp4 ; <ptr> [#uses=1]
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store i32 0, ptr %tmp5
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%tmp7 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=2]
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%0 = icmp sgt i8 %tmp7, 10 ; <i1> [#uses=1]
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br i1 %0, label %return, label %bb
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return: ; preds = %bb
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ret void
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}
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define void @kinds__urangezero(ptr nocapture %a) nounwind {
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; CHECK-LABEL: define void @kinds__urangezero(
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; CHECK-SAME: ptr captures(none) [[A:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: bb.thread:
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; CHECK-NEXT: br label [[BB:%.*]]
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; CHECK: bb:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ [[INDVARS_IV_NEXT:%.*]], [[BB]] ], [ 10, [[BB_THREAD:%.*]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = add nsw i32 [[INDVARS_IV]], -10
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr [21 x i32], ptr [[A]], i32 0, i32 [[TMP4]]
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; CHECK-NEXT: store i32 0, ptr [[TMP5]], align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i32 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[INDVARS_IV_NEXT]], 31
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[RETURN:%.*]], label [[BB]]
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; CHECK: return:
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; CHECK-NEXT: ret void
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;
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bb.thread:
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br label %bb
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bb: ; preds = %bb, %bb.thread
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%i.0.reg2mem.0 = phi i8 [ 10, %bb.thread ], [ %tmp7, %bb ] ; <i8> [#uses=2]
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%tmp12 = sext i8 %i.0.reg2mem.0 to i32 ; <i32> [#uses=1]
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%tmp4 = add i32 %tmp12, -10 ; <i32> [#uses=1]
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%tmp5 = getelementptr [21 x i32], ptr %a, i32 0, i32 %tmp4 ; <ptr> [#uses=1]
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store i32 0, ptr %tmp5
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%tmp7 = add i8 %i.0.reg2mem.0, 1 ; <i8> [#uses=2]
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%0 = icmp sgt i8 %tmp7, 30 ; <i1> [#uses=1]
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br i1 %0, label %return, label %bb
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return: ; preds = %bb
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ret void
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}
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