d309261d05
Miscompilation arises due to instruction combining of cast pairs of the type `bitcast bfloat to half` + `<FPOp> bfloat to half` or `bitcast half to bfloat` + `<FPOp half to bfloat`. For example `bitcast bfloat to half`+`fpext half to double` or `bitcast bfloat to half`+`fpext bfloat to double` respectively reduce to `fpext bfloat to double` and `fpext half to double`. This is an incorrect conversion as it assumes the representation of `bfloat` and `half` are equivalent due to having the same width. As a consequence miscompilation arises. Fixes #61984
88 lines
2.4 KiB
LLVM
88 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -passes=instcombine -S %s | FileCheck %s
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define double @F0(bfloat %P0) {
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; CHECK-LABEL: define double @F0(
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; CHECK-SAME: bfloat [[P0:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV0:%.*]] = bitcast bfloat [[P0]] to half
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; CHECK-NEXT: [[TMP0:%.*]] = fpext half [[CONV0]] to double
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; CHECK-NEXT: ret double [[TMP0]]
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;
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entry:
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%conv0 = bitcast bfloat %P0 to half
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%0 = fpext half %conv0 to double
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ret double %0
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}
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define double @F1(half %P1) {
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; CHECK-LABEL: define double @F1(
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; CHECK-SAME: half [[P1:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV1:%.*]] = bitcast half [[P1]] to bfloat
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; CHECK-NEXT: [[TMP0:%.*]] = fpext bfloat [[CONV1]] to double
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; CHECK-NEXT: ret double [[TMP0]]
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;
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entry:
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%conv1 = bitcast half %P1 to bfloat
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%0 = fpext bfloat %conv1 to double
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ret double %0
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}
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define i32 @F2(bfloat %P2) {
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; CHECK-LABEL: define i32 @F2(
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; CHECK-SAME: bfloat [[P2:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV2:%.*]] = bitcast bfloat [[P2]] to half
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; CHECK-NEXT: [[TMP0:%.*]] = fptoui half [[CONV2]] to i32
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; CHECK-NEXT: ret i32 [[TMP0]]
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;
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entry:
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%conv2 = bitcast bfloat %P2 to half
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%0 = fptoui half %conv2 to i32
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ret i32 %0
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}
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define i32 @F3(half %P3) {
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; CHECK-LABEL: define i32 @F3(
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; CHECK-SAME: half [[P3:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV3:%.*]] = bitcast half [[P3]] to bfloat
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; CHECK-NEXT: [[TMP0:%.*]] = fptoui bfloat [[CONV3]] to i32
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; CHECK-NEXT: ret i32 [[TMP0]]
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;
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entry:
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%conv3 = bitcast half %P3 to bfloat
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%0 = fptoui bfloat %conv3 to i32
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ret i32 %0
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}
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define i32 @F4(bfloat %P4) {
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; CHECK-LABEL: define i32 @F4(
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; CHECK-SAME: bfloat [[P4:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV4:%.*]] = bitcast bfloat [[P4]] to half
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; CHECK-NEXT: [[TMP0:%.*]] = fptosi half [[CONV4]] to i32
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; CHECK-NEXT: ret i32 [[TMP0]]
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;
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entry:
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%conv4 = bitcast bfloat %P4 to half
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%0 = fptosi half %conv4 to i32
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ret i32 %0
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}
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define i32 @F5(half %P5) {
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; CHECK-LABEL: define i32 @F5(
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; CHECK-SAME: half [[P5:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CONV5:%.*]] = bitcast half [[P5]] to bfloat
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; CHECK-NEXT: [[TMP0:%.*]] = fptosi bfloat [[CONV5]] to i32
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; CHECK-NEXT: ret i32 [[TMP0]]
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;
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entry:
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%conv5 = bitcast half %P5 to bfloat
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%0 = fptosi bfloat %conv5 to i32
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ret i32 %0
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}
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