96ab74bf17
Extend `isAllocSiteRemovable` to be able to check if the ModRef info indicates the alloca is only Ref or only Mod, and be able to remove it accordingly. It seemed that there were a surprising number of benchmarks with this pattern which weren't getting optimized previously (due to MemorySSA walk limits). There were somewhat more existing tests than I'd like to have modified which were simply doing exactly this pattern (and thus relying on undef memory). Claude code contributed the new tests (and found an important typo that I'd made). This implements the discussion in https://github.com/llvm/llvm-project/pull/143782#discussion_r2142720376.
44 lines
1.7 KiB
LLVM
44 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=instcombine -S -data-layout="E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64" | FileCheck %s
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define void @PR35618(ptr %st1, ptr %st2, ptr %y1, ptr %z1) {
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; CHECK-LABEL: @PR35618(
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; CHECK-NEXT: [[LD1:%.*]] = load double, ptr [[Y1:%.*]], align 8
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; CHECK-NEXT: [[LD2:%.*]] = load double, ptr [[Z1:%.*]], align 8
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; CHECK-NEXT: [[TMP:%.*]] = fcmp olt double [[LD1]], [[LD2]]
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; CHECK-NEXT: [[TMP12_V:%.*]] = select i1 [[TMP]], double [[LD1]], double [[LD2]]
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; CHECK-NEXT: store double [[TMP12_V]], ptr [[ST1:%.*]], align 8
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; CHECK-NEXT: store double [[TMP12_V]], ptr [[ST2:%.*]], align 8
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; CHECK-NEXT: ret void
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;
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%ld1 = load double, ptr %y1
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%ld2 = load double, ptr %z1
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%tmp = fcmp olt double %ld1, %ld2
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%sel = select i1 %tmp, ptr %y1, ptr %z1
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%tmp12 = load i64, ptr %sel
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store i64 %tmp12, ptr %st1
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store i64 %tmp12, ptr %st2
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ret void
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}
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define void @PR35618_asan(ptr %st1, ptr %st2, ptr %y1, ptr %z1) sanitize_address {
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; CHECK-LABEL: @PR35618_asan(
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; CHECK-NEXT: [[LD1:%.*]] = load double, ptr [[Y1:%.*]], align 8
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; CHECK-NEXT: [[LD2:%.*]] = load double, ptr [[Z1:%.*]], align 8
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; CHECK-NEXT: [[TMP:%.*]] = fcmp olt double [[LD1]], [[LD2]]
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; CHECK-NEXT: [[TMP12_V:%.*]] = select i1 [[TMP]], double [[LD1]], double [[LD2]]
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; CHECK-NEXT: store double [[TMP12_V]], ptr [[ST1:%.*]], align 8
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; CHECK-NEXT: store double [[TMP12_V]], ptr [[ST2:%.*]], align 8
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; CHECK-NEXT: ret void
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;
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%ld1 = load double, ptr %y1
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%ld2 = load double, ptr %z1
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%tmp = fcmp olt double %ld1, %ld2
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%sel = select i1 %tmp, ptr %y1, ptr %z1
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%tmp12 = load i64, ptr %sel
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store i64 %tmp12, ptr %st1
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store i64 %tmp12, ptr %st2
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ret void
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}
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