90ba33099c
This patch canonicalizes getelementptr instructions with constant indices to use the `i8` source element type. This makes it easier for optimizations to recognize that two GEPs are identical, because they don't need to see past many different ways to express the same offset. This is a first step towards https://discourse.llvm.org/t/rfc-replacing-getelementptr-with-ptradd/68699. This is limited to constant GEPs only for now, as they have a clear canonical form, while we're not yet sure how exactly to deal with variable indices. The test llvm/test/Transforms/PhaseOrdering/switch_with_geps.ll gives two representative examples of the kind of optimization improvement we expect from this change. In the first test SimplifyCFG can now realize that all switch branches are actually the same. In the second test it can convert it into simple arithmetic. These are representative of common optimization failures we see in Rust. Fixes https://github.com/llvm/llvm-project/issues/69841.
102 lines
3.5 KiB
LLVM
102 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=instcombine -S < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:4"
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target triple = "x86_64-unknown-linux-gnu"
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define ptr addrspace(4) @f_0() {
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; CHECK-LABEL: @f_0(
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; CHECK-NEXT: ret ptr addrspace(4) getelementptr (i8, ptr addrspace(4) null, i64 50)
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;
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%result = getelementptr i8, ptr addrspace(4) null, i64 50
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ret ptr addrspace(4) %result
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}
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define ptr addrspace(3) @f_1() {
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; inttoptr is fine here since addrspace(3) is integral.
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; CHECK-LABEL: @f_1(
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; CHECK-NEXT: ret ptr addrspace(3) inttoptr (i64 50 to ptr addrspace(3))
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;
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%result = getelementptr i8, ptr addrspace(3) null, i64 50
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ret ptr addrspace(3) %result
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}
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define void @f_2(ptr %ptr0, ptr %ptr1) {
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; It is not okay to convert the load/store pair to load and store
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; integers, since pointers in address space 4 are non-integral.
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; CHECK-LABEL: @f_2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[VAL:%.*]] = load ptr addrspace(4), ptr [[PTR0:%.*]], align 8
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; CHECK-NEXT: store ptr addrspace(4) [[VAL]], ptr [[PTR1:%.*]], align 8
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; CHECK-NEXT: ret void
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;
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entry:
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%val = load ptr addrspace(4), ptr %ptr0
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store ptr addrspace(4) %val, ptr %ptr1
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ret void
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}
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define void @f_3(ptr %ptr0, ptr %ptr1) {
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; It *is* okay to convert the load/store pair to load and store
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; integers, since pointers in address space 3 are integral.
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; CHECK-LABEL: @f_3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[VAL:%.*]] = load ptr addrspace(3), ptr [[PTR0:%.*]], align 8
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; CHECK-NEXT: store ptr addrspace(3) [[VAL]], ptr [[PTR1:%.*]], align 8
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; CHECK-NEXT: ret void
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;
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entry:
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%val = load ptr addrspace(3), ptr %ptr0
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store ptr addrspace(3) %val, ptr %ptr1
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ret void
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}
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define i64 @g(ptr %gp) {
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; CHECK-LABEL: @g(
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; CHECK-NEXT: [[DOTPRE:%.*]] = load ptr addrspace(4), ptr [[GP:%.*]], align 8
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; CHECK-NEXT: [[V74:%.*]] = call ptr addrspace(4) @alloc()
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; CHECK-NEXT: [[V75:%.*]] = addrspacecast ptr addrspace(4) [[V74]] to ptr
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; CHECK-NEXT: [[V77:%.*]] = getelementptr i8, ptr [[V75]], i64 -8
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; CHECK-NEXT: store ptr addrspace(4) [[DOTPRE]], ptr [[V77]], align 8
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; CHECK-NEXT: [[V81:%.*]] = load i64, ptr [[V77]], align 8
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; CHECK-NEXT: ret i64 [[V81]]
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;
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%.pre = load ptr addrspace(4), ptr %gp, align 8
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%v74 = call ptr addrspace(4) @alloc()
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%v75 = addrspacecast ptr addrspace(4) %v74 to ptr
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%v77 = getelementptr ptr addrspace(4), ptr %v75, i64 -1
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store ptr addrspace(4) %.pre, ptr %v77, align 8
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%v81 = load i64, ptr %v77, align 8
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ret i64 %v81
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}
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define i64 @g2(ptr addrspace(4) %gp) {
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; CHECK-LABEL: @g2(
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; CHECK-NEXT: [[DOTPRE:%.*]] = load ptr, ptr addrspace(4) [[GP:%.*]], align 8
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; CHECK-NEXT: [[V74:%.*]] = call ptr addrspace(4) @alloc()
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; CHECK-NEXT: [[V77:%.*]] = getelementptr i8, ptr addrspace(4) [[V74]], i64 -8
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; CHECK-NEXT: store ptr [[DOTPRE]], ptr addrspace(4) [[V77]], align 8
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; CHECK-NEXT: [[V81_CAST:%.*]] = ptrtoint ptr [[DOTPRE]] to i64
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; CHECK-NEXT: ret i64 [[V81_CAST]]
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;
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%.pre = load ptr, ptr addrspace(4) %gp, align 8
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%v74 = call ptr addrspace(4) @alloc()
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%v77 = getelementptr ptr, ptr addrspace(4) %v74, i64 -1
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store ptr %.pre, ptr addrspace(4) %v77, align 8
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%v81 = load i64, ptr addrspace(4) %v77, align 8
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ret i64 %v81
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}
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declare ptr addrspace(4) @alloc()
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define i64 @f_4(ptr addrspace(4) %v0) {
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; CHECK-LABEL: @f_4(
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; CHECK-NEXT: [[V6:%.*]] = call i64 @f_5(ptr addrspace(4) [[V0:%.*]])
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; CHECK-NEXT: ret i64 [[V6]]
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;
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%v6 = call i64 @f_5(ptr addrspace(4) %v0)
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ret i64 %v6
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}
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declare i64 @f_5(i64)
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