b8f3024a31
Since all optimizations that use range metadata now also handle range attribute, this patch replaces writes of range metadata for call instructions to range attributes.
107 lines
4.2 KiB
LLVM
107 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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define i1 @reduce_add_self(<8 x i1> %x) {
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; CHECK-LABEL: @reduce_add_self(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
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; CHECK-NEXT: [[TMP2:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]])
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; CHECK-NEXT: [[RES:%.*]] = trunc i8 [[TMP2]] to i1
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; CHECK-NEXT: ret i1 [[RES]]
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;
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%res = call i1 @llvm.vector.reduce.add.v8i32(<8 x i1> %x)
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ret i1 %res
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}
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define i32 @reduce_add_sext(<4 x i1> %x) {
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; CHECK-LABEL: @reduce_add_sext(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4
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; CHECK-NEXT: [[TMP2:%.*]] = call range(i4 0, 5) i4 @llvm.ctpop.i4(i4 [[TMP1]])
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; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i4 [[TMP2]] to i32
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; CHECK-NEXT: [[RES:%.*]] = sub nsw i32 0, [[TMP3]]
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; CHECK-NEXT: ret i32 [[RES]]
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;
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%sext = sext <4 x i1> %x to <4 x i32>
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%res = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %sext)
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ret i32 %res
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}
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define i64 @reduce_add_zext(<8 x i1> %x) {
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; CHECK-LABEL: @reduce_add_zext(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
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; CHECK-NEXT: [[TMP2:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]])
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; CHECK-NEXT: [[RES:%.*]] = zext nneg i8 [[TMP2]] to i64
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; CHECK-NEXT: ret i64 [[RES]]
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;
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%zext = zext <8 x i1> %x to <8 x i64>
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%res = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %zext)
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ret i64 %res
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}
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define i16 @reduce_add_sext_same(<16 x i1> %x) {
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; CHECK-LABEL: @reduce_add_sext_same(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i1> [[X:%.*]] to i16
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; CHECK-NEXT: [[TMP2:%.*]] = call range(i16 0, 17) i16 @llvm.ctpop.i16(i16 [[TMP1]])
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; CHECK-NEXT: [[RES:%.*]] = sub nsw i16 0, [[TMP2]]
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; CHECK-NEXT: ret i16 [[RES]]
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;
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%sext = sext <16 x i1> %x to <16 x i16>
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%res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %sext)
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ret i16 %res
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}
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define i8 @reduce_add_zext_long(<128 x i1> %x) {
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; CHECK-LABEL: @reduce_add_zext_long(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
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; CHECK-NEXT: [[TMP2:%.*]] = call range(i128 0, 129) i128 @llvm.ctpop.i128(i128 [[TMP1]])
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; CHECK-NEXT: [[TMP3:%.*]] = trunc nuw i128 [[TMP2]] to i8
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; CHECK-NEXT: [[RES:%.*]] = sub i8 0, [[TMP3]]
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; CHECK-NEXT: ret i8 [[RES]]
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;
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%sext = sext <128 x i1> %x to <128 x i8>
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%res = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %sext)
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ret i8 %res
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}
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@glob = external global i8, align 1
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define i8 @reduce_add_zext_long_external_use(<128 x i1> %x) {
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; CHECK-LABEL: @reduce_add_zext_long_external_use(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128
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; CHECK-NEXT: [[TMP2:%.*]] = call range(i128 0, 129) i128 @llvm.ctpop.i128(i128 [[TMP1]])
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; CHECK-NEXT: [[TMP3:%.*]] = trunc nuw i128 [[TMP2]] to i8
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; CHECK-NEXT: [[RES:%.*]] = sub i8 0, [[TMP3]]
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; CHECK-NEXT: [[TMP4:%.*]] = extractelement <128 x i1> [[X]], i64 0
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; CHECK-NEXT: [[EXT:%.*]] = sext i1 [[TMP4]] to i8
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; CHECK-NEXT: store i8 [[EXT]], ptr @glob, align 1
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; CHECK-NEXT: ret i8 [[RES]]
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;
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%sext = sext <128 x i1> %x to <128 x i8>
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%res = call i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %sext)
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%ext = extractelement <128 x i8> %sext, i32 0
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store i8 %ext, ptr @glob, align 1
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ret i8 %res
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}
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@glob1 = external global i64, align 8
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define i64 @reduce_add_zext_external_use(<8 x i1> %x) {
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; CHECK-LABEL: @reduce_add_zext_external_use(
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8
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; CHECK-NEXT: [[TMP2:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]])
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; CHECK-NEXT: [[RES:%.*]] = zext nneg i8 [[TMP2]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i1> [[X]], i64 0
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; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP3]] to i64
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; CHECK-NEXT: store i64 [[EXT]], ptr @glob1, align 8
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; CHECK-NEXT: ret i64 [[RES]]
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;
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%zext = zext <8 x i1> %x to <8 x i64>
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%res = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %zext)
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%ext = extractelement <8 x i64> %zext, i32 0
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store i64 %ext, ptr @glob1, align 8
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ret i64 %res
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}
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declare i1 @llvm.vector.reduce.add.v8i32(<8 x i1> %a)
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declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a)
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declare i64 @llvm.vector.reduce.add.v8i64(<8 x i64> %a)
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declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %a)
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declare i8 @llvm.vector.reduce.add.v128i8(<128 x i8> %a)
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