llvm-project/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-pr49778.ll
Noah Goldstein 2dd52b4527 [InstCombine] Improve logic for adding flags to shift instructions.
Instead of relying on constant operands, use known bits to do the
computation.

Proofs: https://alive2.llvm.org/ce/z/M-aBnw

Differential Revision: https://reviews.llvm.org/D157532
2023-10-12 16:05:19 -05:00

21 lines
698 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
; PR49778: this should not be folded to 0.
define i32 @src(i1 %x2) {
; CHECK-LABEL: @src(
; CHECK-NEXT: [[X13:%.*]] = zext i1 [[X2:%.*]] to i32
; CHECK-NEXT: [[_7:%.*]] = shl nsw i32 -1, [[X13]]
; CHECK-NEXT: [[MASK:%.*]] = xor i32 [[_7]], -1
; CHECK-NEXT: [[_8:%.*]] = and i32 [[MASK]], [[X13]]
; CHECK-NEXT: [[_9:%.*]] = shl nuw nsw i32 [[_8]], [[X13]]
; CHECK-NEXT: ret i32 [[_9]]
;
%x13 = zext i1 %x2 to i32
%_7 = shl i32 4294967295, %x13
%mask = xor i32 %_7, 4294967295
%_8 = and i32 %mask, %x13
%_9 = shl i32 %_8, %x13
ret i32 %_9
}