1f1fd07c32
Currently this optimization only occurs for `mul`, but this generalizes that for any operation that has a fixed point of `0`. There is similar logic within `EarlyCSE` pass, but that is stricter in terms of `poison` propagation so will not optimize for many operations. Alive2 Proofs: `and`: https://alive2.llvm.org/ce/z/RraasX ; base-case https://alive2.llvm.org/ce/z/gzfFTX ; commuted-case https://alive2.llvm.org/ce/z/63XaoX ; compare against undef https://alive2.llvm.org/ce/z/MVRVNd ; select undef https://alive2.llvm.org/ce/z/2bsoYG ; vector https://alive2.llvm.org/ce/z/xByeX- ; vector compare against undef https://alive2.llvm.org/ce/z/zNdzmZ ; vector select undef `fshl`: https://alive2.llvm.org/ce/z/U3_PG3 ; base-case https://alive2.llvm.org/ce/z/BWCnxT ; compare against undef https://alive2.llvm.org/ce/z/8HGAE_ ; select undef ; vector times out `fshr`: https://alive2.llvm.org/ce/z/o6F47G ; base-case https://alive2.llvm.org/ce/z/fVnBXy ; compare against undef https://alive2.llvm.org/ce/z/suymYJ ; select undef ; vector times out `umin`: https://alive2.llvm.org/ce/z/GGMqf6 ; base-case https://alive2.llvm.org/ce/z/6cx5-k ; commuted-case https://alive2.llvm.org/ce/z/W5d9tz ; compare against undef https://alive2.llvm.org/ce/z/nKbaUn ; select undef https://alive2.llvm.org/ce/z/gxEGqc ; vector https://alive2.llvm.org/ce/z/_SDpi_ ; vector compare against undef `sdiv`: https://alive2.llvm.org/ce/z/5XGs3q `srem`: https://alive2.llvm.org/ce/z/vXAnQM `udiv`: https://alive2.llvm.org/ce/z/e6_8Ug `urem`: https://alive2.llvm.org/ce/z/VmM2SL `shl`: https://alive2.llvm.org/ce/z/aCZr3u ; Argument with range https://alive2.llvm.org/ce/z/YgDy8C ; Instruction with known bits https://alive2.llvm.org/ce/z/6pIxR6 ; Constant `lshr`: https://alive2.llvm.org/ce/z/WCCBej `ashr: https://alive2.llvm.org/ce/z/egV4TR --------- Co-authored-by: Ryan Buchner <rbuchner@ventanamicro.com> Co-authored-by: Yingwei Zheng <dtcxzyw@qq.com>
222 lines
7.0 KiB
LLVM
222 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -passes=instcombine < %s | FileCheck %s
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; (select (icmp x, 0, eq), 0, (umin x, y)) -> (umin x, y)
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define i64 @umin_select(i64 %a, i64 %b) {
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; CHECK-LABEL: @umin_select(
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; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
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; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[A:%.*]], i64 [[B_FR]])
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; CHECK-NEXT: ret i64 [[UMIN]]
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;
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%cond = icmp eq i64 %a, 0
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%umin = call i64 @llvm.umin.i64(i64 %a, i64 %b)
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%select = select i1 %cond, i64 0, i64 %umin
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ret i64 %select
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}
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; (select (icmp x, 0, eq), 0, (mul x, y)) -> (mul x, y)
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define i64 @mul_select(i64 %a, i64 %b) {
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; CHECK-LABEL: @mul_select(
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; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
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; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[A:%.*]], [[B_FR]]
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; CHECK-NEXT: ret i64 [[MUL]]
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;
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%cond = icmp eq i64 %a, 0
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%mul = mul i64 %a, %b
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%select = select i1 %cond, i64 0, i64 %mul
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ret i64 %select
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}
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; (select (icmp x, 0, eq), 0, (mul x, y)) -> (mul x, y)
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define i64 @mul_select_comm(i64 %a, i64 %b) {
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; CHECK-LABEL: @mul_select_comm(
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; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
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; CHECK-NEXT: [[MUL:%.*]] = mul i64 [[B_FR]], [[A:%.*]]
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; CHECK-NEXT: ret i64 [[MUL]]
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;
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%cond = icmp eq i64 %a, 0
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%mul = mul i64 %b, %a
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%select = select i1 %cond, i64 0, i64 %mul
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ret i64 %select
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}
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; (select (icmp x, 0, eq), 0, (shl x, y)) -> (shl x, y)
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define i64 @shl_select(i64 %a, i64 %b) {
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; CHECK-LABEL: @shl_select(
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; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
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; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[A]], [[B_FR:%.*]]
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; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[SHL]]
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; CHECK-NEXT: ret i64 [[SELECT]]
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;
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%cond = icmp eq i64 %a, 0
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%shl = shl i64 %a, %b
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%select = select i1 %cond, i64 0, i64 %shl
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ret i64 %select
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}
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; (select (icmp x, 0, eq), 0, (and x, y)) -> (and x, y)
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define i64 @and_select(i64 %a, i64 %b) {
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; CHECK-LABEL: @and_select(
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; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i64 [[A:%.*]], [[B_FR]]
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; CHECK-NEXT: ret i64 [[AND]]
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;
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%cond = icmp eq i64 %a, 0
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%and = and i64 %a, %b
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%select = select i1 %cond, i64 0, i64 %and
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ret i64 %select
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}
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; (select (icmp x, 0, eq), 0, (and x, y)) -> (and x, y)
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define i64 @and_select_comm(i64 %a, i64 %b) {
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; CHECK-LABEL: @and_select_comm(
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; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i64 [[B_FR]], [[A:%.*]]
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; CHECK-NEXT: ret i64 [[AND]]
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;
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%cond = icmp eq i64 %a, 0
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%and = and i64 %b, %a
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%select = select i1 %cond, i64 0, i64 %and
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ret i64 %select
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}
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; (select (icmp x, 0, ne), (ashr x, y), 0) -> (ashr x, y)
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define i64 @ashr_select(i64 %a, i64 %b) {
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; CHECK-LABEL: @ashr_select(
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; CHECK-NEXT: [[COND_NOT:%.*]] = icmp eq i64 [[A:%.*]], 0
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; CHECK-NEXT: [[ASHR:%.*]] = ashr i64 [[A]], [[B_FR:%.*]]
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; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND_NOT]], i64 0, i64 [[ASHR]]
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; CHECK-NEXT: ret i64 [[SELECT]]
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;
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%cond = icmp ne i64 0, %a
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%ashr = ashr i64 %a, %b
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%select = select i1 %cond, i64 %ashr, i64 0
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ret i64 %select
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}
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; (select (icmp x, 0, ne), (lshr x, y), 0) -> (lshr x, y)
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define i64 @lshr_select(i64 %a, i64 %b) {
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; CHECK-LABEL: @lshr_select(
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; CHECK-NEXT: [[COND_NOT:%.*]] = icmp eq i64 [[A:%.*]], 0
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; CHECK-NEXT: [[LSHR:%.*]] = lshr i64 [[A]], [[B_FR:%.*]]
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; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND_NOT]], i64 0, i64 [[LSHR]]
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; CHECK-NEXT: ret i64 [[SELECT]]
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;
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%cond = icmp ne i64 0, %a
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%lshr = lshr i64 %a, %b
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%select = select i1 %cond, i64 %lshr, i64 0
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ret i64 %select
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}
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; (select (icmp x, 0, eq), 0, fshr(x, x, y)) -> fshr(x, x, y)
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define i64 @fshr_select(i64 %a, i64 %b) {
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; CHECK-LABEL: @fshr_select(
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; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
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; CHECK-NEXT: [[FSHR:%.*]] = call i64 @llvm.fshr.i64(i64 [[A:%.*]], i64 [[A]], i64 [[B_FR]])
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; CHECK-NEXT: ret i64 [[FSHR]]
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;
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%cond = icmp eq i64 %a, 0
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%fshr = call i64 @llvm.fshr.i64(i64 %a, i64 %a, i64 %b)
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%select = select i1 %cond, i64 0, i64 %fshr
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ret i64 %select
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}
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; (select (icmp x, 0, eq), 0, (fshl x, x, y)) -> (fshl x, x, y)
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define i64 @fshl_select(i64 %a, i64 %b) {
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; CHECK-LABEL: @fshl_select(
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; CHECK-NEXT: [[B_FR:%.*]] = freeze i64 [[B:%.*]]
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; CHECK-NEXT: [[FSHL:%.*]] = call i64 @llvm.fshl.i64(i64 [[A:%.*]], i64 [[A]], i64 [[B_FR]])
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; CHECK-NEXT: ret i64 [[FSHL]]
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;
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%cond = icmp eq i64 %a, 0
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%fshl = call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %b)
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%select = select i1 %cond, i64 0, i64 %fshl
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ret i64 %select
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}
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; (select (icmp x, 0, eq), 0, (fshr x, z, y)) -> leave as is
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define i64 @fshr_select_no_combine(i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: @fshr_select_no_combine(
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; CHECK-NEXT: [[COND:%.*]] = icmp eq i64 [[A:%.*]], 0
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; CHECK-NEXT: [[FSHR:%.*]] = call i64 @llvm.fshr.i64(i64 [[A]], i64 [[B:%.*]], i64 [[C:%.*]])
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; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[COND]], i64 0, i64 [[FSHR]]
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; CHECK-NEXT: ret i64 [[SELECT]]
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;
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%cond = icmp eq i64 %a, 0
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%fshr = call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 %c)
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%select = select i1 %cond, i64 0, i64 %fshr
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ret i64 %select
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}
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; (select (icmp x, 0, eq), 0, (sdiv x, y)) -> (sdiv x, y)
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define i64 @sdiv_select(i64 %a, i64 %b) {
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; CHECK-LABEL: @sdiv_select(
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 [[A:%.*]], [[B_FR:%.*]]
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; CHECK-NEXT: ret i64 [[DIV]]
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;
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%cond = icmp eq i64 %a, 0
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%div = sdiv i64 %a, %b
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%select = select i1 %cond, i64 0, i64 %div
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ret i64 %select
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}
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; (select (icmp x, 0, eq), 0, (udiv x, y)) -> (udiv x, y)
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define i64 @udiv_select(i64 %a, i64 %b) {
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; CHECK-LABEL: @udiv_select(
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; CHECK-NEXT: [[DIV:%.*]] = udiv i64 [[A:%.*]], [[B_FR:%.*]]
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; CHECK-NEXT: ret i64 [[DIV]]
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;
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%cond = icmp eq i64 %a, 0
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%div = udiv i64 %a, %b
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%select = select i1 %cond, i64 0, i64 %div
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ret i64 %select
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}
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; (select (icmp x, 0, eq), 0, (srem x, y)) -> (srem x, y)
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define i64 @srem_select(i64 %a, i64 %b) {
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; CHECK-LABEL: @srem_select(
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; CHECK-NEXT: [[REM:%.*]] = srem i64 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: ret i64 [[REM]]
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;
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%cond = icmp eq i64 %a, 0
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%rem = srem i64 %a, %b
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%select = select i1 %cond, i64 0, i64 %rem
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ret i64 %select
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}
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; (select (icmp x, 0, eq), 0, (urem x, y)) -> (urem x, y)
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define i64 @urem_select(i64 %a, i64 %b) {
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; CHECK-LABEL: @urem_select(
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; CHECK-NEXT: [[REM:%.*]] = urem i64 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: ret i64 [[REM]]
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;
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%cond = icmp eq i64 %a, 0
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%rem = urem i64 %a, %b
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%select = select i1 %cond, i64 0, i64 %rem
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ret i64 %select
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}
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; (select (icmp x, 0, eq), 0, (icmp x, 0, slt)) -> (icmp x, 0, slt)
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define i1 @icmp_slt_select(i64 %a) {
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; CHECK-LABEL: @icmp_slt_select(
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; CHECK-NEXT: [[ICMP:%.*]] = icmp slt i64 [[A:%.*]], 0
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; CHECK-NEXT: ret i1 [[ICMP]]
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;
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%cond = icmp eq i64 %a, 0
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%icmp = icmp slt i64 %a, 0
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%select = select i1 %cond, i1 0, i1 %icmp
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ret i1 %select
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}
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; (select (icmp x, 0, eq), 0, (sub 0, x)) -> (sub 0, x)
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define i64 @sub_select(i64 %a) {
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; CHECK-LABEL: @sub_select(
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; CHECK-NEXT: [[SUB:%.*]] = sub i64 0, [[A:%.*]]
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; CHECK-NEXT: ret i64 [[SUB]]
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;
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%cond = icmp eq i64 %a, 0
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%sub = sub i64 0, %a
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%select = select i1 %cond, i64 0, i64 %sub
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ret i64 %select
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}
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