236 lines
8.5 KiB
LLVM
236 lines
8.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=instcombine -S < %s | FileCheck %s
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; If we only want bits that already match the signbit then we don't need to shift.
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; https://alive2.llvm.org/ce/z/WJBPVt
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define i32 @src_srem_shl_demand_max_signbit(i32 %a0) {
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; CHECK-LABEL: @src_srem_shl_demand_max_signbit(
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; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 2
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; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SREM]], -2147483648
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; CHECK-NEXT: ret i32 [[MASK]]
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;
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%srem = srem i32 %a0, 2 ; srem = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSD
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%shl = shl i32 %srem, 30 ; shl = SD000000000000000000000000000000
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%mask = and i32 %shl, -2147483648 ; mask = 10000000000000000000000000000000
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ret i32 %mask
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}
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define i32 @src_srem_shl_demand_min_signbit(i32 %a0) {
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; CHECK-LABEL: @src_srem_shl_demand_min_signbit(
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; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 1073741823
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; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SREM]], -2147483648
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; CHECK-NEXT: ret i32 [[MASK]]
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;
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%srem = srem i32 %a0, 1073741823 ; srem = SSDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
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%shl = shl i32 %srem, 1 ; shl = SDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD0
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%mask = and i32 %shl, -2147483648 ; mask = 10000000000000000000000000000000
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ret i32 %mask
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}
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define i32 @src_srem_shl_demand_max_mask(i32 %a0) {
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; CHECK-LABEL: @src_srem_shl_demand_max_mask(
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; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 2
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; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SREM]], -4
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; CHECK-NEXT: ret i32 [[MASK]]
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;
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%srem = srem i32 %a0, 2 ; srem = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSD
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%shl = shl i32 %srem, 1 ; shl = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSD0
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%mask = and i32 %shl, -4 ; mask = 11111111111111111111111111111100
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ret i32 %mask
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}
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; Negative test - mask demands non-signbit from shift source
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define i32 @src_srem_shl_demand_max_signbit_mask_hit_first_demand(i32 %a0) {
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; CHECK-LABEL: @src_srem_shl_demand_max_signbit_mask_hit_first_demand(
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; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 4
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; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SREM]], 29
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; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SHL]], -1073741824
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; CHECK-NEXT: ret i32 [[MASK]]
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;
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%srem = srem i32 %a0, 4 ; srem = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSDD
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%shl = shl i32 %srem, 29 ; shl = SDD00000000000000000000000000000
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%mask = and i32 %shl, -1073741824 ; mask = 11000000000000000000000000000000
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ret i32 %mask
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}
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define i32 @src_srem_shl_demand_min_signbit_mask_hit_last_demand(i32 %a0) {
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; CHECK-LABEL: @src_srem_shl_demand_min_signbit_mask_hit_last_demand(
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; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 536870912
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; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SREM]], 1
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; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SHL]], -1073741822
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; CHECK-NEXT: ret i32 [[MASK]]
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;
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%srem = srem i32 %a0, 536870912 ; srem = SSSDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
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%shl = shl i32 %srem, 1 ; shl = SSDDDDDDDDDDDDDDDDDDDDDDDDDDDDD0
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%mask = and i32 %shl, -1073741822 ; mask = 11000000000000000000000000000010
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ret i32 %mask
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}
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define i32 @src_srem_shl_demand_eliminate_signbit(i32 %a0) {
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; CHECK-LABEL: @src_srem_shl_demand_eliminate_signbit(
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; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 1073741824
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; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SREM]], 1
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; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SHL]], 2
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; CHECK-NEXT: ret i32 [[MASK]]
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;
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%srem = srem i32 %a0, 1073741824 ; srem = SSDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD
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%shl = shl i32 %srem, 1 ; shl = DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD0
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%mask = and i32 %shl, 2 ; mask = 00000000000000000000000000000010
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ret i32 %mask
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}
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define i32 @src_srem_shl_demand_max_mask_hit_demand(i32 %a0) {
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; CHECK-LABEL: @src_srem_shl_demand_max_mask_hit_demand(
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; CHECK-NEXT: [[SREM:%.*]] = srem i32 [[A0:%.*]], 4
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; CHECK-NEXT: [[SHL:%.*]] = shl nsw i32 [[SREM]], 1
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; CHECK-NEXT: [[MASK:%.*]] = and i32 [[SHL]], -4
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; CHECK-NEXT: ret i32 [[MASK]]
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;
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%srem = srem i32 %a0, 4 ; srem = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSDD
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%shl= shl i32 %srem, 1 ; shl = SSSSSSSSSSSSSSSSSSSSSSSSSSSSSDD0
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%mask = and i32 %shl, -4 ; mask = 11111111111111111111111111111100
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ret i32 %mask
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}
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define <2 x i32> @src_srem_shl_mask_vector(<2 x i32> %a0) {
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; CHECK-LABEL: @src_srem_shl_mask_vector(
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; CHECK-NEXT: [[SREM:%.*]] = srem <2 x i32> [[A0:%.*]], splat (i32 4)
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; CHECK-NEXT: [[SHL:%.*]] = shl nsw <2 x i32> [[SREM]], splat (i32 29)
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; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SHL]], splat (i32 -1073741824)
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; CHECK-NEXT: ret <2 x i32> [[MASK]]
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;
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%srem = srem <2 x i32> %a0, <i32 4, i32 4>
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%shl = shl <2 x i32> %srem, <i32 29, i32 29>
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%mask = and <2 x i32> %shl, <i32 -1073741824, i32 -1073741824>
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ret <2 x i32> %mask
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}
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define <2 x i32> @src_srem_shl_mask_vector_nonconstant(<2 x i32> %a0, <2 x i32> %a1) {
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; CHECK-LABEL: @src_srem_shl_mask_vector_nonconstant(
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; CHECK-NEXT: [[SREM:%.*]] = srem <2 x i32> [[A0:%.*]], splat (i32 4)
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; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> [[SREM]], [[A1:%.*]]
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; CHECK-NEXT: [[MASK:%.*]] = and <2 x i32> [[SHL]], splat (i32 -1073741824)
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; CHECK-NEXT: ret <2 x i32> [[MASK]]
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;
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%srem = srem <2 x i32> %a0, <i32 4, i32 4>
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%shl = shl <2 x i32> %srem, %a1
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%mask = and <2 x i32> %shl, <i32 -1073741824, i32 -1073741824>
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ret <2 x i32> %mask
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}
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define i16 @sext_shl_trunc_same_size(i16 %x, i32 %y) {
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; CHECK-LABEL: @sext_shl_trunc_same_size(
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; CHECK-NEXT: [[CONV1:%.*]] = zext i16 [[X:%.*]] to i32
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; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV1]], [[Y:%.*]]
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; CHECK-NEXT: [[T:%.*]] = trunc i32 [[SHL]] to i16
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; CHECK-NEXT: ret i16 [[T]]
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;
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%conv = sext i16 %x to i32
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%shl = shl i32 %conv, %y
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%t = trunc i32 %shl to i16
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ret i16 %t
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}
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define i5 @sext_shl_trunc_smaller(i16 %x, i32 %y) {
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; CHECK-LABEL: @sext_shl_trunc_smaller(
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; CHECK-NEXT: [[CONV1:%.*]] = zext i16 [[X:%.*]] to i32
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; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV1]], [[Y:%.*]]
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; CHECK-NEXT: [[T:%.*]] = trunc i32 [[SHL]] to i5
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; CHECK-NEXT: ret i5 [[T]]
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;
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%conv = sext i16 %x to i32
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%shl = shl i32 %conv, %y
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%t = trunc i32 %shl to i5
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ret i5 %t
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}
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; negative test - demanding 1 high-bit too many to change the extend
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define i17 @sext_shl_trunc_larger(i16 %x, i32 %y) {
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; CHECK-LABEL: @sext_shl_trunc_larger(
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; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[X:%.*]] to i32
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; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV]], [[Y:%.*]]
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; CHECK-NEXT: [[T:%.*]] = trunc i32 [[SHL]] to i17
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; CHECK-NEXT: ret i17 [[T]]
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;
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%conv = sext i16 %x to i32
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%shl = shl i32 %conv, %y
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%t = trunc i32 %shl to i17
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ret i17 %t
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}
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define i32 @sext_shl_mask(i16 %x, i32 %y) {
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; CHECK-LABEL: @sext_shl_mask(
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; CHECK-NEXT: [[CONV1:%.*]] = zext i16 [[X:%.*]] to i32
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; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV1]], [[Y:%.*]]
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; CHECK-NEXT: [[T:%.*]] = and i32 [[SHL]], 65535
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; CHECK-NEXT: ret i32 [[T]]
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;
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%conv = sext i16 %x to i32
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%shl = shl i32 %conv, %y
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%t = and i32 %shl, 65535
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ret i32 %t
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}
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; negative test - demanding a bit that could change with sext
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define i32 @sext_shl_mask_higher(i16 %x, i32 %y) {
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; CHECK-LABEL: @sext_shl_mask_higher(
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; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[X:%.*]] to i32
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; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[CONV]], [[Y:%.*]]
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; CHECK-NEXT: [[T:%.*]] = and i32 [[SHL]], 65536
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; CHECK-NEXT: ret i32 [[T]]
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;
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%conv = sext i16 %x to i32
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%shl = shl i32 %conv, %y
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%t = and i32 %shl, 65536
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ret i32 %t
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}
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; May need some, but not all of the bits set by the 'or'.
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define i32 @set_shl_mask(i32 %x, i32 %y) {
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; CHECK-LABEL: @set_shl_mask(
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; CHECK-NEXT: [[Z:%.*]] = or i32 [[X:%.*]], 65537
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; CHECK-NEXT: [[S:%.*]] = shl i32 [[Z]], [[Y:%.*]]
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; CHECK-NEXT: [[R:%.*]] = and i32 [[S]], 65536
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; CHECK-NEXT: ret i32 [[R]]
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;
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%z = or i32 %x, 196609
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%s = shl i32 %z, %y
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%r = and i32 %s, 65536
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ret i32 %r
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}
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; PR50341
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define i8 @must_drop_poison(i32 %x, i32 %y) {
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; CHECK-LABEL: @must_drop_poison(
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; CHECK-NEXT: [[S:%.*]] = shl i32 [[X:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T:%.*]] = trunc i32 [[S]] to i8
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; CHECK-NEXT: ret i8 [[T]]
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;
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%a = and i32 %x, 255
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%s = shl nuw nsw i32 %a, %y
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%t = trunc i32 %s to i8
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ret i8 %t
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}
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; This would infinite loop with D110170 / bb9333c3504a
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define i32 @f_t15_t01_t09(i40 %t2) {
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; CHECK-LABEL: @f_t15_t01_t09(
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; CHECK-NEXT: [[SH_DIFF:%.*]] = ashr i40 [[T2:%.*]], 15
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; CHECK-NEXT: [[TR_SH_DIFF:%.*]] = trunc nsw i40 [[SH_DIFF]] to i32
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; CHECK-NEXT: [[SHL1:%.*]] = and i32 [[TR_SH_DIFF]], -65536
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; CHECK-NEXT: ret i32 [[SHL1]]
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;
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%downscale = ashr i40 %t2, 31
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%resize = trunc i40 %downscale to i32
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%shl1 = shl i32 %resize, 16
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%resize1 = ashr i32 %shl1, 16
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%r = shl i32 %resize1, 31
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ret i32 %shl1
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}
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