b9808e5660
Loop unrolling tends to produce chains of `%x1 = add %x0, 1; %x2 = add %x1, 1; ...` with one add per unrolled iteration. This patch simplifies these adds to `%xN = add %x0, N` directly during unrolling, rather than waiting for InstCombine to do so. The motivation for this is that having a single add (rather than an add chain) on the induction variable makes it a simple recurrence, which we specially recognize in a number of places. This allows InstCombine to directly perform folds with that knowledge, instead of first folding the add chains, and then doing other folds in another InstCombine iteration. Due to the reduced number of InstCombine iterations, this also results in a small compile-time improvement. Differential Revision: https://reviews.llvm.org/D153540
63 lines
3.0 KiB
LLVM
63 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=loop-unroll -unroll-allow-partial -S %s -verify-loop-info -verify-dom-info -verify-loop-lcssa | FileCheck %s
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@table = internal unnamed_addr global [344 x i32] zeroinitializer, align 16
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define i32 @test_partial_unroll_with_breakout_at_iter0() {
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;
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;
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; CHECK-LABEL: @test_partial_unroll_with_breakout_at_iter0(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_HEADER:%.*]]
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; CHECK: for.header:
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; CHECK-NEXT: [[RED:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[RED_NEXT_3:%.*]], [[FOR_LATCH_3:%.*]] ]
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IV_NEXT_3:%.*]], [[FOR_LATCH_3]] ]
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; CHECK-NEXT: [[RED_NEXT:%.*]] = add nuw nsw i32 10, [[RED]]
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; CHECK-NEXT: [[IV_NEXT:%.*]] = add nuw nsw i64 [[IV]], 2
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; CHECK-NEXT: [[PTR:%.*]] = getelementptr inbounds [344 x i32], ptr @table, i64 0, i64 [[IV_NEXT]]
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; CHECK-NEXT: store i32 [[RED_NEXT]], ptr [[PTR]], align 4
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; CHECK-NEXT: br label [[FOR_LATCH:%.*]]
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; CHECK: for.latch:
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; CHECK-NEXT: [[RED_NEXT_1:%.*]] = add nuw nsw i32 10, [[RED_NEXT]]
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; CHECK-NEXT: [[IV_NEXT_1:%.*]] = add nuw nsw i64 [[IV]], 4
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; CHECK-NEXT: [[PTR_1:%.*]] = getelementptr inbounds [344 x i32], ptr @table, i64 0, i64 [[IV_NEXT_1]]
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; CHECK-NEXT: store i32 [[RED_NEXT_1]], ptr [[PTR_1]], align 4
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; CHECK-NEXT: br label [[FOR_LATCH_1:%.*]]
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; CHECK: for.latch.1:
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; CHECK-NEXT: [[RED_NEXT_2:%.*]] = add nuw nsw i32 10, [[RED_NEXT_1]]
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; CHECK-NEXT: [[IV_NEXT_2:%.*]] = add nuw nsw i64 [[IV]], 6
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; CHECK-NEXT: [[PTR_2:%.*]] = getelementptr inbounds [344 x i32], ptr @table, i64 0, i64 [[IV_NEXT_2]]
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; CHECK-NEXT: store i32 [[RED_NEXT_2]], ptr [[PTR_2]], align 4
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; CHECK-NEXT: br label [[FOR_LATCH_2:%.*]]
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; CHECK: for.latch.2:
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; CHECK-NEXT: [[RED_NEXT_3]] = add nuw nsw i32 10, [[RED_NEXT_2]]
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; CHECK-NEXT: [[IV_NEXT_3]] = add nuw nsw i64 [[IV]], 8
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; CHECK-NEXT: [[PTR_3:%.*]] = getelementptr inbounds [344 x i32], ptr @table, i64 0, i64 [[IV_NEXT_3]]
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; CHECK-NEXT: store i32 [[RED_NEXT_3]], ptr [[PTR_3]], align 4
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; CHECK-NEXT: [[EXITCOND_1_I_3:%.*]] = icmp eq i64 [[IV_NEXT_3]], 344
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; CHECK-NEXT: br i1 [[EXITCOND_1_I_3]], label [[EXIT:%.*]], label [[FOR_LATCH_3]]
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; CHECK: for.latch.3:
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; CHECK-NEXT: br label [[FOR_HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br label %for.header
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for.header: ; preds = %for.body28.i.for.body28.i_crit_edge, %for.body.i
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%red = phi i32 [ 0, %entry ], [ %red.next, %for.latch ]
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %for.latch ]
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%red.next = add i32 10, %red
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%iv.next = add nuw nsw i64 %iv, 2
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%ptr = getelementptr inbounds [344 x i32], ptr @table, i64 0, i64 %iv.next
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store i32 %red.next, ptr %ptr, align 4
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%exitcond.1.i = icmp eq i64 %iv.next, 344
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br i1 %exitcond.1.i, label %exit, label %for.latch
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for.latch: ; preds = %for.header
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br label %for.header
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exit:
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ret i32 0
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}
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