Shilei Tian 84a69a0f8f

[AMDGPU] Move InferAddressSpacesPass to middle end optimization pipeline (#138604) ...

It will run twice in the non-LTO pipeline with `O1` or higher. In LTO post link pipeline, it will be run once with `O2` or higher, since inline and SROA don't run in `O1`.

2025-05-29 17:20:56 -04:00

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infer-address-space.ll

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lit.local.cfg

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