c253e5c991
This patch adds initial vector extension support to RISC-V's exegesis. The strategy here is to enumerate all RVV _pseudo_ opcodes as their MC opcode counterparts are kind of useless under this circumstance. We also enumerate all possible VTYPE operands in each CodeTemplate configuration. Various of MachineFunction Passes are used for post processing the snippets, like inserting VSETVLI instructions. See https://llvm.org/devmtg/2024-10/slides/techtalk/Hsu-RVV-Exegesis.pdf for more technical details.
130 lines
4.0 KiB
C++
130 lines
4.0 KiB
C++
//===- RISCVExegesisPostprocessing.cpp - Post processing MI for exegesis---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// \file
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// This Pass converts some of the virtual register operands in VSETVLI and FRM
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// pseudos into physical registers.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVExegesisPasses.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-exegesis-post-processing"
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namespace {
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struct RISCVExegesisPostprocessing : public MachineFunctionPass {
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static char ID;
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RISCVExegesisPostprocessing() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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// Extremely simple register allocator that picks a register that hasn't
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// been defined or used in this function.
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Register allocateGPRRegister(const MachineFunction &MF,
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const MachineRegisterInfo &MRI);
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bool processVSETVL(MachineInstr &MI, MachineRegisterInfo &MRI);
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bool processWriteFRM(MachineInstr &MI, MachineRegisterInfo &MRI);
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};
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} // anonymous namespace
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char RISCVExegesisPostprocessing::ID = 0;
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bool RISCVExegesisPostprocessing::runOnMachineFunction(MachineFunction &MF) {
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bool Changed = false;
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for (auto &MBB : MF)
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for (auto &MI : MBB) {
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unsigned Opcode = MI.getOpcode();
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switch (Opcode) {
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case RISCV::VSETVLI:
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case RISCV::VSETVL:
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case RISCV::PseudoVSETVLI:
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case RISCV::PseudoVSETVLIX0:
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Changed |= processVSETVL(MI, MF.getRegInfo());
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break;
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case RISCV::SwapFRMImm:
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case RISCV::WriteFRM:
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Changed |= processWriteFRM(MI, MF.getRegInfo());
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break;
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default:
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break;
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}
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}
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if (Changed)
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MF.getRegInfo().clearVirtRegs();
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LLVM_DEBUG(MF.print(dbgs() << "===After RISCVExegesisPostprocessing===\n");
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dbgs() << "\n");
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return Changed;
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}
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Register RISCVExegesisPostprocessing::allocateGPRRegister(
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const MachineFunction &MF, const MachineRegisterInfo &MRI) {
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const auto &TRI = *MRI.getTargetRegisterInfo();
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// We hope to avoid allocating callee-saved registers. And GPRTC
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// happens to account for nearly all caller-saved registers.
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const TargetRegisterClass *GPRClass = TRI.getRegClass(RISCV::GPRTCRegClassID);
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BitVector Candidates = TRI.getAllocatableSet(MF, GPRClass);
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for (unsigned SetIdx : Candidates.set_bits()) {
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if (MRI.reg_empty(Register(SetIdx)))
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return Register(SetIdx);
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}
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// All bets are off, assign a fixed one.
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return RISCV::X5;
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}
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bool RISCVExegesisPostprocessing::processVSETVL(MachineInstr &MI,
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MachineRegisterInfo &MRI) {
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bool Changed = false;
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// Replace both AVL and VL (i.e. the result) operands with physical
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// registers.
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for (unsigned Idx = 0U; Idx < 2; ++Idx)
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if (MI.getOperand(Idx).isReg()) {
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Register RegOp = MI.getOperand(Idx).getReg();
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if (RegOp.isVirtual()) {
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MRI.replaceRegWith(RegOp, allocateGPRRegister(*MI.getMF(), MRI));
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Changed = true;
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}
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}
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return Changed;
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}
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bool RISCVExegesisPostprocessing::processWriteFRM(MachineInstr &MI,
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MachineRegisterInfo &MRI) {
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// The virtual register will be the first operand in both SwapFRMImm and
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// WriteFRM.
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Register DestReg = MI.getOperand(0).getReg();
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if (DestReg.isVirtual()) {
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MRI.replaceRegWith(DestReg, allocateGPRRegister(*MI.getMF(), MRI));
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return true;
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}
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return false;
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}
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FunctionPass *llvm::exegesis::createRISCVPostprocessingPass() {
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return new RISCVExegesisPostprocessing();
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}
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