a5db2c2844
This PR adds support for `-ffine-grained-bitfield-accesses`. I reused
the tests from classic CodeGen, available here:
[c2c881fcc8/clang/test/CodeGenCXX/finegrain-bitfield-access.cpp)
We produce almost exactly the same codegen, except when returning a
variable: we emit an extra variable to hold the return value, whereas
classic CodeGen does not. Also, the GEP instructions use slightly
different syntax compared to classic CodeGen.
272 lines
10 KiB
C++
272 lines
10 KiB
C++
// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir -ffine-grained-bitfield-accesses %s -o %t.cir
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// RUN: FileCheck --input-file=%t.cir %s --check-prefix=CIR
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// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm -ffine-grained-bitfield-accesses %s -o %t-cir.ll
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// RUN: FileCheck --input-file=%t-cir.ll %s --check-prefix=LLVM
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// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm -ffine-grained-bitfield-accesses %s -o %t.ll
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// RUN: FileCheck --input-file=%t.ll %s --check-prefix=OGCG
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struct S1 {
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unsigned f1:2;
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unsigned f2:6;
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unsigned f3:8;
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unsigned f4:4;
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unsigned f5:8;
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};
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// CIR-DAG: !rec_S1 = !cir.record<struct "S1" {!u8i, !u8i, !u16i}>
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// LLVM-DAG: %struct.S1 = type { i8, i8, i16 }
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// OGCG-DAG: %struct.S1 = type { i8, i8, i16 }
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struct S2 {
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unsigned long f1:16;
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unsigned long f2:16;
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unsigned long f3:6;
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};
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// CIR-DAG: !rec_S2 = !cir.record<struct "S2" padded {!u16i, !u16i, !u8i, !cir.array<!u8i x 3>}>
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// LLVM-DAG: %struct.S2 = type { i16, i16, i8, [3 x i8] }
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// OGCG-DAG: %struct.S2 = type { i16, i16, i8, [3 x i8] }
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struct S3 {
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unsigned long f1:14;
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unsigned long f2:18;
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unsigned long f3:32;
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};
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// CIR-DAG: !rec_S3 = !cir.record<struct "S3" {!u32i, !u32i}>
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// LLVM-DAG: %struct.S3 = type { i32, i32 }
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// OGCG-DAG: %struct.S3 = type { i32, i32 }
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S1 a1;
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S2 a2;
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S3 a3;
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unsigned read8_1() {
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return a1.f3;
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}
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// CIR-LABEL: @_Z7read8_1v
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// CIR: [[MEMBER:%.*]] = cir.get_member %1[1] {name = "f3"} : !cir.ptr<!rec_S1> -> !cir.ptr<!u8i>
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// CIR: [[BITFI:%.*]] = cir.get_bitfield align(1) (#bfi_f3, [[MEMBER]] : !cir.ptr<!u8i>) -> !u32i
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// CIR: cir.store [[BITFI]], {{.*}} : !u32i, !cir.ptr<!u32i>
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// CIR: [[RET:%.*]] = cir.load {{.*}} : !cir.ptr<!u32i>, !u32i
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// CIR: cir.return [[RET]] : !u32i
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// LLVM-LABEL: @_Z7read8_1v
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// LLVM: [[MEMBER:%.*]] = load i8, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 1), align 1
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// LLVM: [[BFCAST:%.*]] = zext i8 [[MEMBER]] to i32
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// LLVM: store i32 [[BFCAST]], ptr {{.*}}, align 4
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// LLVM: [[RET:%.*]] = load i32, ptr {{.*}}, align 4
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// LLVM: ret i32 [[RET]]
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// OGCG-LABEL: @_Z7read8_1v
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// OGCG: [[BFLOAD:%.*]] = load i8, ptr getelementptr inbounds nuw (%struct.S1, ptr {{.*}}, i32 0, i32 1), align 1
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// OGCG-NEXT: [[BFCAST:%.*]] = zext i8 [[BFLOAD]] to i32
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// OGCG-NEXT: ret i32 [[BFCAST]]
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void write8_1() {
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a1.f3 = 3;
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}
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// CIR-LABEL: @_Z8write8_1v
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// CIR: [[CONST3:%.*]] = cir.const #cir.int<3> : !s32i
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// CIR: [[INT3:%.*]] = cir.cast(integral, [[CONST3]] : !s32i), !u32i
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// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[1] {name = "f3"} : !cir.ptr<!rec_S1> -> !cir.ptr<!u8i>
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// CIR: cir.set_bitfield align(1) (#bfi_f3, [[MEMBER]] : !cir.ptr<!u8i>, [[INT3]] : !u32i) -> !u32i
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// LLVM-LABEL: @_Z8write8_1v
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// LLVM: store i8 3, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 1), align 1
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// LLVM: ret void
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// OGCG-LABEL: @_Z8write8_1v
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// OGCG: store i8 3, ptr getelementptr inbounds nuw (%struct.S1, ptr {{.*}}, i32 0, i32 1), align 1
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// OGCG-NEXT: ret void
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unsigned read8_2() {
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return a1.f5;
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}
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// CIR-LABEL: @_Z7read8_2v
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// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[2] {name = "f5"} : !cir.ptr<!rec_S1> -> !cir.ptr<!u16i>
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// CIR: [[BITFI:%.*]] = cir.get_bitfield align(2) (#bfi_f5, [[MEMBER]] : !cir.ptr<!u16i>) -> !u32i
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// CIR: cir.store [[BITFI]], {{.*}} : !u32i, !cir.ptr<!u32i>
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// CIR: [[RET:%.*]] = cir.load {{.*}} : !cir.ptr<!u32i>, !u32i
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// CIR: cir.return [[RET]] : !u32i
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// LLVM-LABEL: @_Z7read8_2v
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// LLVM: [[BFLOAD:%.*]] = load i16, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 2), align 2
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// LLVM: [[BFLSHR:%.*]] = lshr i16 [[BFLOAD]], 4
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// LLVM: [[BFCLEAR:%.*]] = and i16 [[BFLSHR]], 255
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// LLVM: [[BFCAST:%.*]] = zext i16 [[BFCLEAR]] to i32
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// LLVM: store i32 [[BFCAST]], ptr {{.*}}, align 4
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// LLVM: [[RET:%.*]] = load i32, ptr {{.*}}, align 4
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// LLVM: ret i32 [[RET]]
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// OGCG-LABEL: @_Z7read8_2v
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// OGCG: [[BFLOAD:%.*]] = load i16, ptr getelementptr inbounds nuw (%struct.S1, ptr {{.*}}, i32 0, i32 2), align 2
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// OGCG-NEXT: [[BFLSHR:%.*]] = lshr i16 [[BFLOAD]], 4
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// OGCG-NEXT: [[BFCLEAR:%.*]] = and i16 [[BFLSHR]], 255
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// OGCG-NEXT: [[BFCAST:%.*]] = zext i16 [[BFCLEAR]] to i32
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// OGCG-NEXT: ret i32 [[BFCAST]]
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void write8_2() {
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a1.f5 = 3;
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}
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// CIR-LABEL: @_Z8write8_2v
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// CIR: [[CONST3:%.*]] = cir.const #cir.int<3> : !s32i
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// CIR: [[INT3:%.*]] = cir.cast(integral, [[CONST3]] : !s32i), !u32i
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// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[2] {name = "f5"} : !cir.ptr<!rec_S1> -> !cir.ptr<!u16i>
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// CIR: cir.set_bitfield align(2) (#bfi_f5, %3 : !cir.ptr<!u16i>, {{.*}} : !u32i) -> !u32i
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// LLVM-LABEL: @_Z8write8_2v
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// LLVM: [[BFLOAD:%.*]] = load i16, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 2), align 2
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// LLVM: [[BFCLEAR:%.*]] = and i16 [[BFLOAD]], -4081
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// LLVM: [[BFSET:%.*]] = or i16 [[BFCLEAR]], 48
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// LLVM: store i16 [[BFSET]], ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 2), align 2
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// LLVM: ret void
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// OGCG-LABEL: @_Z8write8_2v
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// OGCG: [[BFLOAD:%.*]] = load i16, ptr getelementptr inbounds nuw (%struct.S1, ptr {{.*}}, i32 0, i32 2), align 2
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// OGCG-NEXT: [[BFCLEAR:%.*]] = and i16 [[BFLOAD]], -4081
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// OGCG-NEXT: [[BFSET:%.*]] = or i16 [[BFCLEAR]], 48
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// OGCG-NEXT: store i16 [[BFSET]], ptr getelementptr inbounds nuw (%struct.S1, ptr {{.*}}, i32 0, i32 2), align 2
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// OGCG-NEXT: ret void
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unsigned read16_1() {
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return a2.f1;
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}
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// CIR-LABEL: @_Z8read16_1v
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// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[0] {name = "f1"} : !cir.ptr<!rec_S2> -> !cir.ptr<!u16i>
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// CIR: [[BITFI:%.*]] = cir.get_bitfield align(8) (#bfi_f1, [[MEMBER]] : !cir.ptr<!u16i>) -> !u64i
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// CIR: [[BFCAST:%.*]] = cir.cast(integral, [[BITFI]] : !u64i), !u32i
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// CIR: cir.store [[BFCAST]], {{.*}} : !u32i, !cir.ptr<!u32i>
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// CIR: [[RET:%.*]] = cir.load {{.*}} : !cir.ptr<!u32i>, !u32i
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// CIR: cir.return [[RET]] : !u32i
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// LLVM-LABEL: @_Z8read16_1v
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// LLVM: [[BFLOAD:%.*]] = load i16, ptr {{.*}}, align 8
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// LLVM: [[BFCAST:%.*]] = zext i16 [[BFLOAD]] to i64
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// LLVM: [[BF:%.*]] = trunc i64 [[BFCAST]] to i32
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// LLVM: store i32 [[BF]], ptr {{.*}}, align 4
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// LLVM: [[RET:%.*]] = load i32, ptr {{.*}}, align 4
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// LLVM: ret i32 [[RET]]
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// OGCG-LABEL: @_Z8read16_1v
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// OGCG: [[BFLOAD:%.*]] = load i16, ptr {{.*}}, align 8
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// OGCG-NEXT: [[BFCAST:%.*]] = zext i16 [[BFLOAD]] to i64
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// OGCG-NEXT: [[RET:%.*]] = trunc i64 [[BFCAST]] to i32
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// OGCG-NEXT: ret i32 [[RET]]
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unsigned read16_2() {
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return a2.f2;
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}
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// CIR-LABEL: @_Z8read16_2v
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// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[1] {name = "f2"} : !cir.ptr<!rec_S2> -> !cir.ptr<!u16i>
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// CIR: [[BITFI:%.*]] = cir.get_bitfield align(2) (#bfi_f2, [[MEMBER]] : !cir.ptr<!u16i>) -> !u64i
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// CIR: [[BFCAST:%.*]] = cir.cast(integral, [[BITFI]] : !u64i), !u32i
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// CIR: cir.store [[BFCAST]], {{.*}} : !u32i, !cir.ptr<!u32i>
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// CIR: [[RET:%.*]] = cir.load {{.*}} : !cir.ptr<!u32i>, !u32i
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// CIR: cir.return [[RET]] : !u32i
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// LLVM-LABEL: @_Z8read16_2v
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// LLVM: [[BFLOAD:%.*]] = load i16, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 2), align 2
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// LLVM: [[BFCAST:%.*]] = zext i16 [[BFLOAD]] to i64
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// LLVM: [[BF:%.*]] = trunc i64 [[BFCAST]] to i32
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// LLVM: store i32 [[BF]], ptr {{.*}}, align 4
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// LLVM: [[RET:%.*]] = load i32, ptr {{.*}}, align 4
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// LLVM: ret i32 [[RET]]
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// OGCG-LABEL: @_Z8read16_2v
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// OGCG: [[BFLOAD:%.*]] = load i16, ptr getelementptr inbounds nuw (%struct.S2, ptr {{.*}}, i32 0, i32 1), align 2
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// OGCG-NEXT: [[BFCAST:%.*]] = zext i16 [[BFLOAD]] to i64
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// OGCG-NEXT: [[RET:%.*]] = trunc i64 [[BFCAST]] to i32
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// OGCG-NEXT: ret i32 [[RET]]
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void write16_1() {
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a2.f1 = 5;
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}
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// CIR-LABEL: @_Z9write16_1v
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// CIR: [[CONST5:%.*]] = cir.const #cir.int<5> : !s32i
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// CIR: [[INT5:%.*]] = cir.cast(integral, [[CONST5]] : !s32i), !u64i
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// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[0] {name = "f1"} : !cir.ptr<!rec_S2> -> !cir.ptr<!u16i>
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// CIR: cir.set_bitfield align(8) (#bfi_f1, [[MEMBER]] : !cir.ptr<!u16i>, [[INT5]] : !u64i) -> !u64i
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// CIR: cir.return
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// LLVM-LABEL: @_Z9write16_1v
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// LLVM: store i16 5, ptr {{.*}}, align 8
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// LLVM: ret void
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// OGCG-LABEL: @_Z9write16_1v
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// OGCG: store i16 5, ptr {{.*}}, align 8
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// OGCG-NEXT: ret void
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void write16_2() {
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a2.f2 = 5;
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}
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// CIR-LABEL: @_Z9write16_2v
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// CIR: [[CONST5:%.*]] = cir.const #cir.int<5> : !s32i
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// CIR: [[INT5:%.*]] = cir.cast(integral, [[CONST5]] : !s32i), !u64i
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// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[1] {name = "f2"} : !cir.ptr<!rec_S2> -> !cir.ptr<!u16i>
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// CIR: cir.set_bitfield align(2) (#bfi_f2, [[MEMBER]] : !cir.ptr<!u16i>, {{.*}} : !u64i) -> !u64i
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// CIR: cir.return
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// LLVM-LABEL: @_Z9write16_2v
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// LLVM: store i16 5, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 2), align 2
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// LLVM: ret void
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// OGCG-LABEL: @_Z9write16_2v
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// OGCG: store i16 5, ptr getelementptr inbounds nuw (%struct.S2, ptr {{.*}}, i32 0, i32 1), align 2
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// OGCG-NEXT: ret void
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unsigned read32_1() {
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return a3.f3;
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}
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// CIR-LABEL: @_Z8read32_1v
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// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[1] {name = "f3"} : !cir.ptr<!rec_S3> -> !cir.ptr<!u32i>
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// CIR: [[BITFI:%.*]] = cir.get_bitfield align(4) (#bfi_f3_1, [[MEMBER]] : !cir.ptr<!u32i>) -> !u64i
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// CIR: [[BFCAST:%.*]] = cir.cast(integral, [[BITFI]] : !u64i), !u32i
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// CIR: cir.store [[BFCAST]], {{.*}} : !u32i, !cir.ptr<!u32i>
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// CIR: [[RET:%.*]] = cir.load {{.*}} : !cir.ptr<!u32i>, !u32i
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// CIR: cir.return [[RET]] : !u32i
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// LLVM-LABEL: @_Z8read32_1v
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// LLVM: [[BFLOAD:%.*]] = load i32, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 4), align 4
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// LLVM: [[BFCAST:%.*]] = zext i32 [[BFLOAD]] to i64
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// LLVM: [[BF:%.*]] = trunc i64 [[BFCAST]] to i32
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// LLVM: store i32 [[BF]], ptr {{.*}}, align 4
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// LLVM: [[RET:%.*]] = load i32, ptr {{.*}}, align 4
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// LLVM: ret i32 [[RET]]
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// OGCG-LABEL: @_Z8read32_1v
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// OGCG: [[BFLOAD:%.*]] = load i32, ptr getelementptr inbounds nuw (%struct.S3, ptr {{.*}}, i32 0, i32 1), align 4
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// OGCG-NEXT: [[BFCAST:%.*]] = zext i32 %bf.load to i64
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// OGCG-NEXT: [[RET:%.*]] = trunc i64 %bf.cast to i32
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// OGCG-NEXT: ret i32 [[RET]]
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void write32_1() {
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a3.f3 = 5;
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}
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// CIR-LABEL: @_Z9write32_1v
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// CIR: [[CONST5:%.*]] = cir.const #cir.int<5> : !s32i
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// CIR: [[INT5:%.*]] = cir.cast(integral, [[CONST5]] : !s32i), !u64i
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// CIR: [[MEMBER:%.*]] = cir.get_member {{.*}}[1] {name = "f3"} : !cir.ptr<!rec_S3> -> !cir.ptr<!u32i>
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// CIR: cir.set_bitfield align(4) (#bfi_f3_1, [[MEMBER]] : !cir.ptr<!u32i>, [[INT5]] : !u64i) -> !u64i
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// CIR: cir.return
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// LLVM-LABEL: @_Z9write32_1v
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// LLVM: store i32 5, ptr getelementptr inbounds nuw (i8, ptr {{.*}}, i64 4), align 4
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// LLVM: ret void
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// OGCG-LABEL: @_Z9write32_1v
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// OGCG: store i32 5, ptr getelementptr inbounds nuw (%struct.S3, ptr {{.*}}, i32 0, i32 1), align 4
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// OGCG-NEXT: ret void
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