474f5d2aef
These cannot be detected by reading the ID_AA64ISAR1_EL1 register since their corresponding bitfields are hidden. Additionally the instructions that these features enable are unusable from EL0. ACLE: https://github.com/ARM-software/acle/pull/382
68 lines
2.7 KiB
C
68 lines
2.7 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals --global-value-regex ".*"
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s
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//.
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// CHECK: @__aarch64_cpu_features = external dso_local global { i64 }
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//.
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// CHECK-LABEL: @main(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
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// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70368744177664
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// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70368744177664
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// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
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// CHECK-NEXT: br i1 [[TMP3]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
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// CHECK: if.then:
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// CHECK-NEXT: store i32 1, ptr [[RETVAL]], align 4
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// CHECK-NEXT: br label [[RETURN:%.*]]
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// CHECK: if.end:
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// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 17936857268992
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// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 17936857268992
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// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
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// CHECK-NEXT: br i1 [[TMP7]], label [[IF_THEN1:%.*]], label [[IF_END2:%.*]]
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// CHECK: if.then1:
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// CHECK-NEXT: store i32 2, ptr [[RETVAL]], align 4
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// CHECK-NEXT: br label [[RETURN]]
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// CHECK: if.end2:
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// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8
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// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 162133984766132992
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// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 162133984766132992
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// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
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// CHECK-NEXT: br i1 [[TMP11]], label [[IF_THEN3:%.*]], label [[IF_END4:%.*]]
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// CHECK: if.then3:
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// CHECK-NEXT: store i32 3, ptr [[RETVAL]], align 4
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// CHECK-NEXT: br label [[RETURN]]
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// CHECK: if.end4:
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// CHECK-NEXT: br i1 false, label [[IF_THEN5:%.*]], label [[IF_END6:%.*]]
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// CHECK: if.then5:
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// CHECK-NEXT: store i32 4, ptr [[RETVAL]], align 4
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// CHECK-NEXT: br label [[RETURN]]
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// CHECK: if.end6:
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// CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
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// CHECK-NEXT: br label [[RETURN]]
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// CHECK: return:
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// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[RETVAL]], align 4
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// CHECK-NEXT: ret i32 [[TMP12]]
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//
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int main(void) {
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if (__builtin_cpu_supports("sb"))
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return 1;
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if (__builtin_cpu_supports("sve2-aes+memtag"))
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return 2;
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if (__builtin_cpu_supports("sme2+wfxt"))
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return 3;
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if (__builtin_cpu_supports("avx2"))
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return 4;
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return 0;
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}
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//.
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// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
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// CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
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//.
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