5fdd094837
In the beginning, Clang only emitted atomic IR for operations it knew the underlying microarch had instructions for, meaning it required significant knowledge of the target. Later, the backend acquired the ability to lower IR to libcalls. To avoid duplicating logic and improve logic locality, we'd like to move as much as possible to the backend. There are many ways to describe this change. For example, this change reduces the variables Clang uses to decide whether to emit libcalls or IR, down to only the atomic's size.
85 lines
3.1 KiB
C
85 lines
3.1 KiB
C
// RUN: %clang_cc1 -Werror -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
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// RUN: -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s \
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// RUN: --check-prefixes=PPC64,PPC64-QUADWORD-ATOMICS
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// RUN: %clang_cc1 -Werror -Wno-atomic-alignment -triple powerpc64le-linux-gnu \
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// RUN: -emit-llvm -o - %s | FileCheck %s \
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// RUN: --check-prefixes=PPC64,PPC64-NO-QUADWORD-ATOMICS
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// RUN: %clang_cc1 -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
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// RUN: -target-cpu pwr7 -emit-llvm -o - %s | FileCheck %s \
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// RUN: --check-prefixes=PPC64,PPC64-NO-QUADWORD-ATOMICS
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// RUN: %clang_cc1 -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
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// RUN: -target-cpu pwr8 -emit-llvm -o - %s | FileCheck %s \
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// RUN: --check-prefixes=PPC64,PPC64-NO-QUADWORD-ATOMICS
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// RUN: %clang_cc1 -Werror -Wno-atomic-alignment -triple powerpc64-unknown-aix \
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// RUN: -mabi=quadword-atomics -target-cpu pwr8 -emit-llvm -o - %s | \
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// RUN: FileCheck %s --check-prefixes=PPC64,PPC64-QUADWORD-ATOMICS
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typedef struct {
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char x[16];
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} Q;
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typedef _Atomic(Q) AtomicQ;
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typedef __int128_t int128_t;
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// PPC64-LABEL: @test_load(
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// PPC64: [[TMP3:%.*]] = load atomic i128, ptr [[TMP1:%.*]] acquire, align 16
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//
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Q test_load(AtomicQ *ptr) {
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// expected-no-diagnostics
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return __c11_atomic_load(ptr, __ATOMIC_ACQUIRE);
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}
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// PPC64-LABEL: @test_store(
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// PPC64: store atomic i128 [[TMP6:%.*]], ptr [[TMP4:%.*]] release, align 16
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//
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void test_store(Q val, AtomicQ *ptr) {
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// expected-no-diagnostics
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__c11_atomic_store(ptr, val, __ATOMIC_RELEASE);
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}
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// PPC64-LABEL: @test_add(
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// PPC64: [[ATOMICRMW:%.*]] = atomicrmw add ptr [[TMP0:%.*]], i128 [[TMP2:%.*]] monotonic, align 16
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//
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void test_add(_Atomic(int128_t) *ptr, int128_t x) {
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// expected-no-diagnostics
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__c11_atomic_fetch_add(ptr, x, __ATOMIC_RELAXED);
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}
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// PPC64-LABEL: @test_xchg(
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// PPC64: [[TMP8:%.*]] = atomicrmw xchg ptr [[TMP4:%.*]], i128 [[TMP7:%.*]] seq_cst, align 16
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//
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Q test_xchg(AtomicQ *ptr, Q new) {
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// expected-no-diagnostics
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return __c11_atomic_exchange(ptr, new, __ATOMIC_SEQ_CST);
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}
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// PPC64-LABEL: @test_cmpxchg(
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// PPC64: [[TMP10:%.*]] = cmpxchg ptr [[TMP5:%.*]], i128 [[TMP8:%.*]], i128 [[TMP9:%.*]] seq_cst monotonic, align 16
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//
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int test_cmpxchg(AtomicQ *ptr, Q *cmp, Q new) {
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// expected-no-diagnostics
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return __c11_atomic_compare_exchange_strong(ptr, cmp, new, __ATOMIC_SEQ_CST, __ATOMIC_RELAXED);
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}
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// PPC64-LABEL: @test_cmpxchg_weak(
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// PPC64: [[TMP10:%.*]] = cmpxchg weak ptr [[TMP5:%.*]], i128 [[TMP8:%.*]], i128 [[TMP9:%.*]] seq_cst monotonic, align 16
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//
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int test_cmpxchg_weak(AtomicQ *ptr, Q *cmp, Q new) {
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// expected-no-diagnostics
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return __c11_atomic_compare_exchange_weak(ptr, cmp, new, __ATOMIC_SEQ_CST, __ATOMIC_RELAXED);
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}
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// PPC64-QUADWORD-ATOMICS-LABEL: @is_lock_free(
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// PPC64-QUADWORD-ATOMICS: ret i32 1
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//
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// PPC64-NO-QUADWORD-ATOMICS-LABEL: @is_lock_free(
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// PPC64-NO-QUADWORD-ATOMICS: [[CALL:%.*]] = call zeroext i1 @__atomic_is_lock_free(i64 noundef 16, ptr noundef null)
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//
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int is_lock_free() {
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AtomicQ q;
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// expected-no-diagnostics
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return __c11_atomic_is_lock_free(sizeof(q));
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}
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