f3bf8e0166
Adds missing C++ run lines to test files containing `constexpr` tests. Also adds missing 32/64-bit test coverage to the following tests: - `clang/test/CodeGen/X86/avx512-reduceIntrin.c` - `clang/test/CodeGen/X86/avx512-reduceMinMaxIntrin.c` - `clang/test/CodeGen/X86/avx512vpopcntdq-builtins.c` - `clang/test/CodeGen/X86/avx512vpopcntdqvl-builtins.c` Additionally, fixes a `_mm512_popcnt_epi64` `constexpr` test that incorrectly assumed 32-bit integers, leading to incorrect bit counts. This change updates the test result to assume 64-bit integers.
176 lines
8.0 KiB
C
176 lines
8.0 KiB
C
// RUN: %clang_cc1 -x c -ffreestanding %s -O0 -triple=x86_64-apple-darwin -target-cpu skylake-avx512 -emit-llvm -o - -Wall -Werror | FileCheck %s
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// RUN: %clang_cc1 -x c -ffreestanding %s -O0 -triple=i386-apple-darwin -target-cpu skylake-avx512 -emit-llvm -o - -Wall -Werror | FileCheck %s
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// RUN: %clang_cc1 -x c++ -ffreestanding %s -O0 -triple=x86_64-apple-darwin -target-cpu skylake-avx512 -emit-llvm -o - -Wall -Werror | FileCheck %s
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// RUN: %clang_cc1 -x c++ -ffreestanding %s -O0 -triple=i386-apple-darwin -target-cpu skylake-avx512 -emit-llvm -o - -Wall -Werror | FileCheck %s
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#include <immintrin.h>
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#include "builtin_test_helpers.h"
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long long test_mm512_reduce_max_epi64(__m512i __W){
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// CHECK-LABEL: test_mm512_reduce_max_epi64
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// CHECK: call {{.*}}i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> %{{.*}})
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return _mm512_reduce_max_epi64(__W);
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}
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TEST_CONSTEXPR(_mm512_reduce_max_epi64((__m512i)(__v8di){-4, -3, -2, -1, 0, 1, 2, 3}) == 3);
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unsigned long long test_mm512_reduce_max_epu64(__m512i __W){
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// CHECK-LABEL: test_mm512_reduce_max_epu64
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// CHECK: call {{.*}}i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> %{{.*}})
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return _mm512_reduce_max_epu64(__W);
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}
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TEST_CONSTEXPR(_mm512_reduce_max_epu64((__m512i)(__v8du){0, 1, 2, 3, 4, 5, 6, 7}) == 7);
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double test_mm512_reduce_max_pd(__m512d __W, double ExtraAddOp){
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// CHECK-LABEL: test_mm512_reduce_max_pd
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// CHECK-NOT: nnan
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// CHECK: call nnan {{.*}}double @llvm.vector.reduce.fmax.v8f64(<8 x double> %{{.*}})
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// CHECK-NOT: nnan
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return _mm512_reduce_max_pd(__W) + ExtraAddOp;
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}
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long long test_mm512_reduce_min_epi64(__m512i __W){
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// CHECK-LABEL: test_mm512_reduce_min_epi64
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// CHECK: call {{.*}}i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> %{{.*}})
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return _mm512_reduce_min_epi64(__W);
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}
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TEST_CONSTEXPR(_mm512_reduce_min_epi64((__m512i)(__v8di){-4, -3, -2, -1, 0, 1, 2, 3}) == -4);
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unsigned long long test_mm512_reduce_min_epu64(__m512i __W){
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// CHECK-LABEL: test_mm512_reduce_min_epu64
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// CHECK: call {{.*}}i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> %{{.*}})
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return _mm512_reduce_min_epu64(__W);
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}
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TEST_CONSTEXPR(_mm512_reduce_min_epu64((__m512i)(__v8du){0, 1, 2, 3, 4, 5, 6, 7}) == 0);
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double test_mm512_reduce_min_pd(__m512d __W, double ExtraMulOp){
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// CHECK-LABEL: test_mm512_reduce_min_pd
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// CHECK-NOT: nnan
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// CHECK: call nnan {{.*}}double @llvm.vector.reduce.fmin.v8f64(<8 x double> %{{.*}})
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// CHECK-NOT: nnan
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return _mm512_reduce_min_pd(__W) * ExtraMulOp;
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}
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long long test_mm512_mask_reduce_max_epi64(__mmask8 __M, __m512i __W){
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// CHECK-LABEL: test_mm512_mask_reduce_max_epi64
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// CHECK: select <8 x i1> %{{.*}}, <8 x i64> %{{.*}}, <8 x i64> %{{.*}}
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// CHECK: call {{.*}}i64 @llvm.vector.reduce.smax.v8i64(<8 x i64> %{{.*}})
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return _mm512_mask_reduce_max_epi64(__M, __W);
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}
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unsigned long test_mm512_mask_reduce_max_epu64(__mmask8 __M, __m512i __W){
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// CHECK-LABEL: test_mm512_mask_reduce_max_epu64
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// CHECK: select <8 x i1> %{{.*}}, <8 x i64> %{{.*}}, <8 x i64> %{{.*}}
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// CHECK: call {{.*}}i64 @llvm.vector.reduce.umax.v8i64(<8 x i64> %{{.*}})
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return _mm512_mask_reduce_max_epu64(__M, __W);
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}
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double test_mm512_mask_reduce_max_pd(__mmask8 __M, __m512d __W){
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// CHECK-LABEL: test_mm512_mask_reduce_max_pd
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// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
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// CHECK: call nnan {{.*}}double @llvm.vector.reduce.fmax.v8f64(<8 x double> %{{.*}})
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return _mm512_mask_reduce_max_pd(__M, __W);
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}
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long long test_mm512_mask_reduce_min_epi64(__mmask8 __M, __m512i __W){
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// CHECK-LABEL: test_mm512_mask_reduce_min_epi64
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// CHECK: select <8 x i1> %{{.*}}, <8 x i64> %{{.*}}, <8 x i64> %{{.*}}
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// CHECK: call {{.*}}i64 @llvm.vector.reduce.smin.v8i64(<8 x i64> %{{.*}})
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return _mm512_mask_reduce_min_epi64(__M, __W);
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}
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unsigned long long test_mm512_mask_reduce_min_epu64(__mmask8 __M, __m512i __W){
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// CHECK-LABEL: test_mm512_mask_reduce_min_epu64
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// CHECK: select <8 x i1> %{{.*}}, <8 x i64> %{{.*}}, <8 x i64> %{{.*}}
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// CHECK: call {{.*}}i64 @llvm.vector.reduce.umin.v8i64(<8 x i64> %{{.*}})
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return _mm512_mask_reduce_min_epu64(__M, __W);
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}
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double test_mm512_mask_reduce_min_pd(__mmask8 __M, __m512d __W){
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// CHECK-LABEL: test_mm512_mask_reduce_min_pd
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// CHECK: select <8 x i1> %{{.*}}, <8 x double> %{{.*}}, <8 x double> %{{.*}}
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// CHECK: call nnan {{.*}}double @llvm.vector.reduce.fmin.v8f64(<8 x double> %{{.*}})
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return _mm512_mask_reduce_min_pd(__M, __W);
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}
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int test_mm512_reduce_max_epi32(__m512i __W){
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// CHECK-LABEL: test_mm512_reduce_max_epi32
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// CHECK: call {{.*}}i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %{{.*}})
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return _mm512_reduce_max_epi32(__W);
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}
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TEST_CONSTEXPR(_mm512_reduce_max_epi32((__m512i)(__v16si){-8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7}) == 7);
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unsigned int test_mm512_reduce_max_epu32(__m512i __W){
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// CHECK-LABEL: test_mm512_reduce_max_epu32
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// CHECK: call {{.*}}i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %{{.*}})
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return _mm512_reduce_max_epu32(__W);
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}
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TEST_CONSTEXPR(_mm512_reduce_max_epu32((__m512i)(__v16su){0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}) == 15);
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float test_mm512_reduce_max_ps(__m512 __W){
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// CHECK-LABEL: test_mm512_reduce_max_ps
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// CHECK: call nnan {{.*}}float @llvm.vector.reduce.fmax.v16f32(<16 x float> %{{.*}})
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return _mm512_reduce_max_ps(__W);
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}
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int test_mm512_reduce_min_epi32(__m512i __W){
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// CHECK-LABEL: test_mm512_reduce_min_epi32
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// CHECK: call {{.*}}i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> %{{.*}})
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return _mm512_reduce_min_epi32(__W);
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}
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TEST_CONSTEXPR(_mm512_reduce_min_epi32((__m512i)(__v16si){-8, -7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7}) == -8);
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unsigned int test_mm512_reduce_min_epu32(__m512i __W){
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// CHECK-LABEL: test_mm512_reduce_min_epu32
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// CHECK: call {{.*}}i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %{{.*}})
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return _mm512_reduce_min_epu32(__W);
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}
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TEST_CONSTEXPR(_mm512_reduce_min_epu32((__m512i)(__v16su){0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}) == 0);
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float test_mm512_reduce_min_ps(__m512 __W){
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// CHECK-LABEL: test_mm512_reduce_min_ps
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// CHECK: call nnan {{.*}}float @llvm.vector.reduce.fmin.v16f32(<16 x float> %{{.*}})
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return _mm512_reduce_min_ps(__W);
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}
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int test_mm512_mask_reduce_max_epi32(__mmask16 __M, __m512i __W){
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// CHECK-LABEL: test_mm512_mask_reduce_max_epi32
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// CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
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// CHECK: call {{.*}}i32 @llvm.vector.reduce.smax.v16i32(<16 x i32> %{{.*}})
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return _mm512_mask_reduce_max_epi32(__M, __W);
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}
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unsigned int test_mm512_mask_reduce_max_epu32(__mmask16 __M, __m512i __W){
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// CHECK-LABEL: test_mm512_mask_reduce_max_epu32
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// CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
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// CHECK: call {{.*}}i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %{{.*}})
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return _mm512_mask_reduce_max_epu32(__M, __W);
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}
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float test_mm512_mask_reduce_max_ps(__mmask16 __M, __m512 __W){
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// CHECK-LABEL: test_mm512_mask_reduce_max_ps
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// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
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// CHECK: call nnan {{.*}}float @llvm.vector.reduce.fmax.v16f32(<16 x float> %{{.*}})
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return _mm512_mask_reduce_max_ps(__M, __W);
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}
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int test_mm512_mask_reduce_min_epi32(__mmask16 __M, __m512i __W){
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// CHECK-LABEL: test_mm512_mask_reduce_min_epi32
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// CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
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// CHECK: call {{.*}}i32 @llvm.vector.reduce.smin.v16i32(<16 x i32> %{{.*}})
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return _mm512_mask_reduce_min_epi32(__M, __W);
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}
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unsigned int test_mm512_mask_reduce_min_epu32(__mmask16 __M, __m512i __W){
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// CHECK-LABEL: test_mm512_mask_reduce_min_epu32
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// CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
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// CHECK: call {{.*}}i32 @llvm.vector.reduce.umin.v16i32(<16 x i32> %{{.*}})
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return _mm512_mask_reduce_min_epu32(__M, __W);
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}
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float test_mm512_mask_reduce_min_ps(__mmask16 __M, __m512 __W){
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// CHECK-LABEL: test_mm512_mask_reduce_min_ps
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// CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
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// CHECK: call nnan {{.*}}float @llvm.vector.reduce.fmin.v16f32(<16 x float> %{{.*}})
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return _mm512_mask_reduce_min_ps(__M, __W);
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}
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