06da00ae2d
`+simd` and `+nosimd` are used to enable or disable NEON Instructions when compiling for ARM Targets. However, up until now, using these has not been possible. To enable this, these options are mapped to the relevant LLVM backend option (`+neon` and `-neon`) so it can be both enabled and disabled successfully by the user. Tests have been added to ensure this behaviour is maintained in the future, along with updates to existing tests as behaviour has now changed relating to the use of `+simd` and `+nosimd`. As `simd` has been mapped within the ARMTargetParser.def, support for this extension is also added for the `--print-support-extensions` command when the target is AArch32. This will print the `simd` option, along with the description that relates to the Neon feature. This previously was not possible as `simd` did not have a related Feature or Negative Feature. To make this functional as intended, MVE and MVE.FP now rely on their own Enum identifier, rather than `AEK_SIMD`. While SIMD does refer to both Neon and Helium technologies, in terms of command line options, SIMD relates to Neon. Helium relates to MVE and MVE.FP. The Enum now reflects this too.
32 lines
2.2 KiB
C
32 lines
2.2 KiB
C
// REQUIRES: arm-registered-target
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// RUN: %clang --target=arm-linux-gnu --print-supported-extensions | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s
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// CHECK: All available -march extensions for ARM
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// CHECK-EMPTY:
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// CHECK-NEXT: Name Description
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// CHECK-NEXT: crc Enable support for CRC instructions
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// CHECK-NEXT: crypto Enable support for Cryptography extensions
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// CHECK-NEXT: sha2 Enable SHA1 and SHA256 support
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// CHECK-NEXT: aes Enable AES support
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// CHECK-NEXT: dotprod Enable support for dot product instructions
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// CHECK-NEXT: dsp Supports DSP instructions in ARM and/or Thumb2
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// CHECK-NEXT: mve Support M-Class Vector Extension with integer ops
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// CHECK-NEXT: mve.fp Support M-Class Vector Extension with integer and floating ops
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// CHECK-NEXT: simd Enable NEON instructions
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// CHECK-NEXT: fp16 Enable half-precision floating point
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// CHECK-NEXT: ras Enable Reliability, Availability and Serviceability extensions
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// CHECK-NEXT: fp16fml Enable full half-precision floating point fml instructions
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// CHECK-NEXT: bf16 Enable support for BFloat16 instructions
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// CHECK-NEXT: sb Enable v8.5a Speculation Barrier
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// CHECK-NEXT: i8mm Enable Matrix Multiply Int8 Extension
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// CHECK-NEXT: lob Enable Low Overhead Branch extensions
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// CHECK-NEXT: cdecp0 Coprocessor 0 ISA is CDEv1
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// CHECK-NEXT: cdecp1 Coprocessor 1 ISA is CDEv1
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// CHECK-NEXT: cdecp2 Coprocessor 2 ISA is CDEv1
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// CHECK-NEXT: cdecp3 Coprocessor 3 ISA is CDEv1
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// CHECK-NEXT: cdecp4 Coprocessor 4 ISA is CDEv1
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// CHECK-NEXT: cdecp5 Coprocessor 5 ISA is CDEv1
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// CHECK-NEXT: cdecp6 Coprocessor 6 ISA is CDEv1
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// CHECK-NEXT: cdecp7 Coprocessor 7 ISA is CDEv1
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// CHECK-NEXT: pacbti Enable Pointer Authentication and Branch Target Identification
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