2f9c97c030
Andes AX45MPV is 64-bit in-order dual-issue 8-stage pipeline linux-capable CPU implementing the RV64IMAFDCV ISA extension. That is developed by Andes Technology https://www.andestech.com, a RISC-V IP provider. The overviews for AX45MPV: https://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mpv/ Scheduling model for RVV extension will be implemented a follow-up PR.
126 lines
5.2 KiB
C
126 lines
5.2 KiB
C
// This test uses '<prefix>-SAME: {{^}}' to start matching immediately where the
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// previous check finished matching (specifically, caret is not treated as
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// matching a start of line when used like this in FileCheck).
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// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
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// RISCV32: error: unknown target CPU 'not-a-cpu'
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// RISCV32-NEXT: note: valid target CPU values are:
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// RISCV32-SAME: {{^}} andes-a25
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// RISCV32-SAME: {{^}}, andes-a45
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// RISCV32-SAME: {{^}}, andes-n45
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// RISCV32-SAME: {{^}}, generic-rv32
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// RISCV32-SAME: {{^}}, rocket-rv32
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// RISCV32-SAME: {{^}}, rp2350-hazard3
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// RISCV32-SAME: {{^}}, sifive-e20
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// RISCV32-SAME: {{^}}, sifive-e21
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// RISCV32-SAME: {{^}}, sifive-e24
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// RISCV32-SAME: {{^}}, sifive-e31
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// RISCV32-SAME: {{^}}, sifive-e34
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// RISCV32-SAME: {{^}}, sifive-e76
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// RISCV32-SAME: {{^}}, syntacore-scr1-base
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// RISCV32-SAME: {{^}}, syntacore-scr1-max
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// RISCV32-SAME: {{^}}, syntacore-scr3-rv32
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// RISCV32-SAME: {{^}}, syntacore-scr4-rv32
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// RISCV32-SAME: {{^}}, syntacore-scr5-rv32
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// RISCV32-SAME: {{$}}
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// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
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// RISCV64: error: unknown target CPU 'not-a-cpu'
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// RISCV64-NEXT: note: valid target CPU values are:
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// RISCV64-SAME: {{^}} andes-ax25
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// RISCV64-SAME: {{^}}, andes-ax45
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// RISCV64-SAME: {{^}}, andes-ax45mpv
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// RISCV64-SAME: {{^}}, andes-nx45
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// RISCV64-SAME: {{^}}, generic-rv64
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// RISCV64-SAME: {{^}}, mips-p8700
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// RISCV64-SAME: {{^}}, rocket-rv64
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// RISCV64-SAME: {{^}}, sifive-p450
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// RISCV64-SAME: {{^}}, sifive-p470
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// RISCV64-SAME: {{^}}, sifive-p550
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// RISCV64-SAME: {{^}}, sifive-p670
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// RISCV64-SAME: {{^}}, sifive-p870
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// RISCV64-SAME: {{^}}, sifive-s21
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// RISCV64-SAME: {{^}}, sifive-s51
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// RISCV64-SAME: {{^}}, sifive-s54
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// RISCV64-SAME: {{^}}, sifive-s76
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// RISCV64-SAME: {{^}}, sifive-u54
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// RISCV64-SAME: {{^}}, sifive-u74
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// RISCV64-SAME: {{^}}, sifive-x280
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// RISCV64-SAME: {{^}}, sifive-x390
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// RISCV64-SAME: {{^}}, spacemit-x60
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// RISCV64-SAME: {{^}}, syntacore-scr3-rv64
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// RISCV64-SAME: {{^}}, syntacore-scr4-rv64
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// RISCV64-SAME: {{^}}, syntacore-scr5-rv64
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// RISCV64-SAME: {{^}}, syntacore-scr7
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// RISCV64-SAME: {{^}}, tt-ascalon-d8
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// RISCV64-SAME: {{^}}, veyron-v1
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// RISCV64-SAME: {{^}}, xiangshan-kunminghu
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// RISCV64-SAME: {{^}}, xiangshan-nanhu
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// RISCV64-SAME: {{$}}
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// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
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// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV32-NEXT: note: valid target CPU values are:
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// TUNE-RISCV32-SAME: {{^}} andes-a25
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// TUNE-RISCV32-SAME: {{^}}, andes-a45
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// TUNE-RISCV32-SAME: {{^}}, andes-n45
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// TUNE-RISCV32-SAME: {{^}}, generic-rv32
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// TUNE-RISCV32-SAME: {{^}}, rocket-rv32
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// TUNE-RISCV32-SAME: {{^}}, rp2350-hazard3
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// TUNE-RISCV32-SAME: {{^}}, sifive-e20
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// TUNE-RISCV32-SAME: {{^}}, sifive-e21
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// TUNE-RISCV32-SAME: {{^}}, sifive-e24
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// TUNE-RISCV32-SAME: {{^}}, sifive-e31
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// TUNE-RISCV32-SAME: {{^}}, sifive-e34
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// TUNE-RISCV32-SAME: {{^}}, sifive-e76
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// TUNE-RISCV32-SAME: {{^}}, syntacore-scr1-base
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// TUNE-RISCV32-SAME: {{^}}, syntacore-scr1-max
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// TUNE-RISCV32-SAME: {{^}}, syntacore-scr3-rv32
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// TUNE-RISCV32-SAME: {{^}}, syntacore-scr4-rv32
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// TUNE-RISCV32-SAME: {{^}}, syntacore-scr5-rv32
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// TUNE-RISCV32-SAME: {{^}}, andes-45-series
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// TUNE-RISCV32-SAME: {{^}}, generic
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// TUNE-RISCV32-SAME: {{^}}, generic-ooo
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// TUNE-RISCV32-SAME: {{^}}, rocket
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// TUNE-RISCV32-SAME: {{^}}, sifive-7-series
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// TUNE-RISCV32-SAME: {{$}}
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// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
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// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV64-NEXT: note: valid target CPU values are:
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// TUNE-RISCV64-SAME: {{^}} andes-ax25
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// TUNE-RISCV64-SAME: {{^}}, andes-ax45
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// TUNE-RISCV64-SAME: {{^}}, andes-ax45mpv
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// TUNE-RISCV64-SAME: {{^}}, andes-nx45
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// TUNE-RISCV64-SAME: {{^}}, generic-rv64
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// TUNE-RISCV64-SAME: {{^}}, mips-p8700
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// TUNE-RISCV64-SAME: {{^}}, rocket-rv64
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// TUNE-RISCV64-SAME: {{^}}, sifive-p450
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// TUNE-RISCV64-SAME: {{^}}, sifive-p470
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// TUNE-RISCV64-SAME: {{^}}, sifive-p550
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// TUNE-RISCV64-SAME: {{^}}, sifive-p670
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// TUNE-RISCV64-SAME: {{^}}, sifive-p870
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// TUNE-RISCV64-SAME: {{^}}, sifive-s21
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// TUNE-RISCV64-SAME: {{^}}, sifive-s51
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// TUNE-RISCV64-SAME: {{^}}, sifive-s54
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// TUNE-RISCV64-SAME: {{^}}, sifive-s76
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// TUNE-RISCV64-SAME: {{^}}, sifive-u54
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// TUNE-RISCV64-SAME: {{^}}, sifive-u74
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// TUNE-RISCV64-SAME: {{^}}, sifive-x280
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// TUNE-RISCV64-SAME: {{^}}, sifive-x390
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// TUNE-RISCV64-SAME: {{^}}, spacemit-x60
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// TUNE-RISCV64-SAME: {{^}}, syntacore-scr3-rv64
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// TUNE-RISCV64-SAME: {{^}}, syntacore-scr4-rv64
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// TUNE-RISCV64-SAME: {{^}}, syntacore-scr5-rv64
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// TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
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// TUNE-RISCV64-SAME: {{^}}, tt-ascalon-d8
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// TUNE-RISCV64-SAME: {{^}}, veyron-v1
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// TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu
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// TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
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// TUNE-RISCV64-SAME: {{^}}, andes-45-series
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// TUNE-RISCV64-SAME: {{^}}, generic
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// TUNE-RISCV64-SAME: {{^}}, generic-ooo
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// TUNE-RISCV64-SAME: {{^}}, rocket
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// TUNE-RISCV64-SAME: {{^}}, sifive-7-series
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// TUNE-RISCV64-SAME: {{$}}
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