42e79d9771
This allows the user to set the size of the scalable vector so they can be used in structs and as the type of global variables. This works by representing the type as a fixed vector instead of a scalable vector in IR. Conversions to and from scalable vectors are made where necessary like function arguments/returns and intrinsics. This features has been requested here https://github.com/riscv-non-isa/rvv-intrinsic-doc/issues/176 I know arm_sve_vector_bits is used by the Eigen library so this could be used to port Eigen to RVV. This patch adds a new preprocessor define `__riscv_v_fixed_vlen` that is set when -mrvv_vector_bits is passed on the command line. The code is largely based on the AArch64 code. A lot of code was copy/pasted and then modiied to RVV. There may be some opportunities for sharing. This first patch only supports the LMUL=1 types. Additional changes will be needed to support other LMULs. I have also not supported mask vectors. Differential Revision: https://reviews.llvm.org/D145088
60 lines
2.7 KiB
C
60 lines
2.7 KiB
C
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=1 -mvscale-max=1 -flax-vector-conversions=none -ffreestanding -fsyntax-only -verify %s
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// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=2 -mvscale-max=2 -flax-vector-conversions=none -ffreestanding -fsyntax-only -verify %s
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// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 -flax-vector-conversions=none -ffreestanding -fsyntax-only -verify %s
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// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 -flax-vector-conversions=none -ffreestanding -fsyntax-only -verify %s
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// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=16 -mvscale-max=16 -flax-vector-conversions=none -ffreestanding -fsyntax-only -verify %s
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// expected-no-diagnostics
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// REQUIRES: riscv-registered-target
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#define FIXED_ATTR __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)))
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typedef __rvv_int8m1_t vint8m1_t;
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typedef __rvv_uint8m1_t vuint8m1_t;
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typedef __rvv_int16m1_t vint16m1_t;
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typedef __rvv_uint16m1_t vuint16m1_t;
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typedef __rvv_int32m1_t vint32m1_t;
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typedef __rvv_uint32m1_t vuint32m1_t;
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typedef __rvv_int64m1_t vint64m1_t;
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typedef __rvv_uint64m1_t vuint64m1_t;
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typedef __rvv_float32m1_t vfloat32m1_t;
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typedef __rvv_float64m1_t vfloat64m1_t;
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typedef vfloat32m1_t fixed_float32m1_t FIXED_ATTR;
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typedef vfloat64m1_t fixed_float64m1_t FIXED_ATTR;
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typedef vint32m1_t fixed_int32m1_t FIXED_ATTR;
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typedef vint64m1_t fixed_int64m1_t FIXED_ATTR;
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// RVV VLS types can be cast to RVV VLA types, regardless of lane size.
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// NOTE: the list below is NOT exhaustive for all RVV types.
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#define CAST(from, to) \
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void from##_to_##to(from a, to b) { \
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b = (to) a; \
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}
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#define TESTCASE(ty1, ty2) \
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CAST(ty1, ty2) \
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CAST(ty2, ty1)
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TESTCASE(fixed_float32m1_t, vfloat32m1_t)
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TESTCASE(fixed_float32m1_t, vfloat64m1_t)
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TESTCASE(fixed_float32m1_t, vint32m1_t)
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TESTCASE(fixed_float32m1_t, vint64m1_t)
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TESTCASE(fixed_float64m1_t, vfloat32m1_t)
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TESTCASE(fixed_float64m1_t, vfloat64m1_t)
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TESTCASE(fixed_float64m1_t, vint32m1_t)
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TESTCASE(fixed_float64m1_t, vint64m1_t)
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TESTCASE(fixed_int32m1_t, vfloat32m1_t)
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TESTCASE(fixed_int32m1_t, vfloat64m1_t)
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TESTCASE(fixed_int32m1_t, vint32m1_t)
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TESTCASE(fixed_int32m1_t, vint64m1_t)
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TESTCASE(fixed_int64m1_t, vfloat32m1_t)
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TESTCASE(fixed_int64m1_t, vfloat64m1_t)
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TESTCASE(fixed_int64m1_t, vint32m1_t)
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TESTCASE(fixed_int64m1_t, vint64m1_t)
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