9312d5beb3
Current approach generates intrinsic records when users specify corresponding required features by using command line option. However it's not able to handle features passed by using target attributes correctly where each function might have different features. This patch resolves this by generating all of intrinsic records which carry the required features in their function declaration using attribute and check the required extensions in CheckBuiltinFunctionCall. This should fix [56592](https://github.com/llvm/llvm-project/issues/56592), [134962](https://github.com/llvm/llvm-project/issues/134962) and [121603](https://github.com/llvm/llvm-project/issues/121603)
36 lines
1004 B
C
36 lines
1004 B
C
// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -triple riscv64 -target-feature +zvknha %s -fsyntax-only -verify
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#include <riscv_vector.h>
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// expected-no-diagnostics
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__attribute__((target("arch=+zvl128b")))
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void test_zvk_features(vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) {
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__riscv_vsha2ch_vv_u32m1(vd, vs2, vs1, vl);
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}
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__attribute__((target("arch=+v,+zvkn")))
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vuint32m4_t testcase1(vuint32m4_t pt, vuint32m1_t rk, size_t vl)
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{
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return __riscv_vaesz_vs_u32m1_u32m4(pt, rk, vl);
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}
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__attribute__((target("arch=+v,+zvknc")))
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vuint32m4_t testcase2(vuint32m4_t pt, vuint32m1_t rk, size_t vl)
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{
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return __riscv_vaesz_vs_u32m1_u32m4(pt, rk, vl);
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}
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__attribute__((target("arch=+v,+zvkned")))
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vuint32m4_t testcase3(vuint32m4_t pt, vuint32m1_t rk, size_t vl)
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{
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return __riscv_vaesz_vs_u32m1_u32m4(pt, rk, vl);
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}
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__attribute__((target("arch=+v,+zvkng")))
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vuint32m4_t testcase4(vuint32m4_t pt, vuint32m1_t rk, size_t vl)
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{
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return __riscv_vaesz_vs_u32m1_u32m4(pt, rk, vl);
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}
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