f122268c04
Using OtherPredicates for True16 predicates is often problematic due to interference with other kinds of predicates, particularly when this overrides predicates inherited from pseudo instructions.
55 lines
1.5 KiB
TableGen
55 lines
1.5 KiB
TableGen
//===-- R600.td - R600 Tablegen files ----------------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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def R600InstrInfo : InstrInfo {
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let guessInstructionProperties = 1;
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}
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def R600 : Target {
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let InstructionSet = R600InstrInfo;
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let AllowRegisterRenaming = 1;
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}
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let Namespace = "R600" in {
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foreach Index = 0-15 in {
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def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
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}
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include "R600RegisterInfo.td"
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}
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def NullALU : InstrItinClass;
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def ALU_NULL : FuncUnit;
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include "AMDGPUFeatures.td"
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include "R600Schedule.td"
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include "R600Processors.td"
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include "R600InstrInfo.td"
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include "AMDGPUInstrInfo.td"
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include "AMDGPUPredicateControl.td"
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include "AMDGPUInstructions.td"
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include "R600Instructions.td"
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include "R700Instructions.td"
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include "EvergreenInstructions.td"
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include "CaymanInstructions.td"
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// Calling convention for R600
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def CC_R600 : CallingConv<[
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CCIfInReg<CCIfType<[v4f32, v4i32] , CCAssignToReg<[
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T0_XYZW, T1_XYZW, T2_XYZW, T3_XYZW, T4_XYZW, T5_XYZW, T6_XYZW, T7_XYZW,
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T8_XYZW, T9_XYZW, T10_XYZW, T11_XYZW, T12_XYZW, T13_XYZW, T14_XYZW, T15_XYZW,
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T16_XYZW, T17_XYZW, T18_XYZW, T19_XYZW, T20_XYZW, T21_XYZW, T22_XYZW,
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T23_XYZW, T24_XYZW, T25_XYZW, T26_XYZW, T27_XYZW, T28_XYZW, T29_XYZW,
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T30_XYZW, T31_XYZW, T32_XYZW
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]>>>
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]>;
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