a47c35a699
The createSIMachineScheduler & createPostMachineScheduler target hooks are currently placed in the PassConfig interface. Moving it out to TargetMachine so that both legacy and the new pass manager can effectively use them.
78 lines
2.9 KiB
C++
78 lines
2.9 KiB
C++
//===-- R600TargetMachine.h - AMDGPU TargetMachine Interface ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// The AMDGPU TargetMachine interface definition for hw codegen targets.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_R600TARGETMACHINE_H
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#define LLVM_LIB_TARGET_AMDGPU_R600TARGETMACHINE_H
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#include "AMDGPUTargetMachine.h"
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#include "R600Subtarget.h"
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#include "llvm/Target/TargetMachine.h"
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#include <optional>
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namespace llvm {
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//===----------------------------------------------------------------------===//
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// R600 Target Machine (R600 -> Cayman)
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//===----------------------------------------------------------------------===//
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class R600TargetMachine final : public AMDGPUTargetMachine {
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private:
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mutable StringMap<std::unique_ptr<R600Subtarget>> SubtargetMap;
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public:
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R600TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
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bool JIT);
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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Error buildCodeGenPipeline(ModulePassManager &MPM, raw_pwrite_stream &Out,
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raw_pwrite_stream *DwoOut,
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CodeGenFileType FileType,
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const CGPassBuilderOption &Opt,
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PassInstrumentationCallbacks *PIC) override;
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const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override;
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TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
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bool isMachineVerifierClean() const override { return false; }
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MachineFunctionInfo *
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createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
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const TargetSubtargetInfo *STI) const override;
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ScheduleDAGInstrs *
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createMachineScheduler(MachineSchedContext *C) const override;
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};
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//===----------------------------------------------------------------------===//
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// R600 CodeGen Pass Builder interface.
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//===----------------------------------------------------------------------===//
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class R600CodeGenPassBuilder
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: public CodeGenPassBuilder<R600CodeGenPassBuilder, R600TargetMachine> {
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public:
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R600CodeGenPassBuilder(R600TargetMachine &TM, const CGPassBuilderOption &Opts,
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PassInstrumentationCallbacks *PIC);
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void addPreISel(AddIRPass &addPass) const;
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void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const;
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Error addInstSelector(AddMachinePass &) const;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_R600TARGETMACHINE_H
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