3d1705d00c
Allows MCExprs as passed values to PALMetadata. Also adds related `DelayedMCExpr` classes which serve as a pseudo-fixup to resolve MCExprs as late as possible (i.e., right before emit through string or blob, where they should be resolvable).
80 lines
2.8 KiB
C++
80 lines
2.8 KiB
C++
//===-- SIDefines.h - SI Helper Functions -----------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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/// \file - utility functions for the SIDefines and its common uses.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_SIDEFINESUTILS_H
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#define LLVM_LIB_TARGET_AMDGPU_UTILS_SIDEFINESUTILS_H
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#include "llvm/MC/MCExpr.h"
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#include <utility>
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namespace llvm {
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class MCContext;
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namespace AMDGPU {
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/// Deduce the least significant bit aligned shift and mask values for a binary
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/// Complement \p Value (as they're defined in SIDefines.h as C_*) as a returned
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/// pair<shift, mask>. That is to say \p Value == ~(mask << shift)
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///
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/// For example, given C_00B848_FWD_PROGRESS (i.e., 0x7FFFFFFF) from
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/// SIDefines.h, this will return the pair as (31,1).
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constexpr std::pair<unsigned, unsigned> getShiftMask(unsigned Value) {
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unsigned Shift = 0;
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unsigned Mask = 0;
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Mask = ~Value;
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for (; !(Mask & 1); Shift++, Mask >>= 1) {
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}
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return std::make_pair(Shift, Mask);
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}
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/// Provided with the MCExpr * \p Val, uint32 \p Mask and \p Shift, will return
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/// the masked and left shifted, in said order of operations, MCExpr * created
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/// within the MCContext \p Ctx.
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///
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/// For example, given MCExpr *Val, Mask == 0xf, Shift == 6 the returned MCExpr
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/// * will be the equivalent of (Val & 0xf) << 6
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inline const MCExpr *maskShiftSet(const MCExpr *Val, uint32_t Mask,
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uint32_t Shift, MCContext &Ctx) {
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if (Mask) {
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const MCExpr *MaskExpr = MCConstantExpr::create(Mask, Ctx);
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Val = MCBinaryExpr::createAnd(Val, MaskExpr, Ctx);
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}
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if (Shift) {
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const MCExpr *ShiftExpr = MCConstantExpr::create(Shift, Ctx);
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Val = MCBinaryExpr::createShl(Val, ShiftExpr, Ctx);
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}
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return Val;
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}
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/// Provided with the MCExpr * \p Val, uint32 \p Mask and \p Shift, will return
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/// the right shifted and masked, in said order of operations, MCExpr * created
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/// within the MCContext \p Ctx.
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///
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/// For example, given MCExpr *Val, Mask == 0xf, Shift == 6 the returned MCExpr
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/// * will be the equivalent of (Val >> 6) & 0xf
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inline const MCExpr *maskShiftGet(const MCExpr *Val, uint32_t Mask,
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uint32_t Shift, MCContext &Ctx) {
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if (Shift) {
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const MCExpr *ShiftExpr = MCConstantExpr::create(Shift, Ctx);
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Val = MCBinaryExpr::createLShr(Val, ShiftExpr, Ctx);
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}
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if (Mask) {
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const MCExpr *MaskExpr = MCConstantExpr::create(Mask, Ctx);
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Val = MCBinaryExpr::createAnd(Val, MaskExpr, Ctx);
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}
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return Val;
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}
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} // end namespace AMDGPU
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_SIDEFINESUTILS_H
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