aff98e4be0
1. When two (or more) nodes are glued, DAG scheduler will always
schedule them as one piece, i.e. it will not allow any instructions to
be scheduled between them. It does so because if nodes are glued this
usually means that there is an implicit register dependency between
them, and an intervening node could clobber this physical register. When
emitting such nodes into machine IR, they will also be stuck together,
e.g.:
```
%9:gpr = MOVsrl_glue killed %8, implicit-def $cpsr
%10:gpr = RRX %3, implicit $cpsr
```
2. If a node has Glue result, SelectionDAG will not try to CSE this
node. If it did, it would break the implicit physical register
dependency. In practice this means that if a node with Glue result has
multiple uses, it has to be duplicated before each use. This the reason
for `ARMTargetLowering::duplicateCmp` to exist.
When using normal data dependency, dependent nodes can freely be
scheduled around. If there is a physical register dependency between
nodes, the physical register will be copied to/from a virtual register,
allowing other nodes to intervene between them. The resulting machine IR
might look like this:
```
%9:gpr = LSRs1 killed %8, implicit-def $cpsr
%10:gpr = COPY $cpsr
%11:gpr = ORRrsi killed %9, %3, 242, 14 /* CC::al */, $noreg, $noreg
%12:gpr = BICri killed %11, -2147483648, 14 /* CC::al */, $noreg, $noreg
$cpsr = COPY %10
%13:gpr = RRX %3, implicit $cpsr
```
The two copies are likely to be eliminated by register coalescer, given
that there are no instructions between them that clobber this physical
register. If the copies are unwanted in the first place (they could be
expensive or impossible), DAG scheduler will try to avoid inserting them
wherever possible, and the resulting machine IR will look like this:
```
%9:gpr = LSRs1 killed %8, implicit-def $cpsr
%10:gpr = ORRrsi killed %9, %3, 242, 14 /* CC::al */, $noreg, $noreg
%11:gpr = BICri killed %10, -2147483648, 14 /* CC::al */, $noreg, $noreg
%12:gpr = RRX %3, implicit $cpsr
```
On ARM, arithmetic operations and LSLS already use the new data flow
approach. This patch extends it to include 1-bit shifts.
Pull Request: https://github.com/llvm/llvm-project/pull/116547
496 lines
19 KiB
TableGen
496 lines
19 KiB
TableGen
//=- ARMScheduleM7.td - ARM Cortex-M7 Scheduling Definitions -*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the SchedRead/Write data for the ARM Cortex-M7 processor.
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//
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//===----------------------------------------------------------------------===//
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def CortexM7Model : SchedMachineModel {
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let IssueWidth = 2; // Dual issue for most instructions.
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let MicroOpBufferSize = 0; // The Cortex-M7 is in-order.
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let LoadLatency = 2; // Best case for load-use case.
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let MispredictPenalty = 4; // Mispredict cost for forward branches is 6,
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// but 4 works better
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let CompleteModel = 0;
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}
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let SchedModel = CortexM7Model in {
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//===--------------------------------------------------------------------===//
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// The Cortex-M7 has two ALU, two LOAD, a STORE, a MAC, a BRANCH and a VFP
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// pipe. The stages relevant to scheduling are as follows:
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//
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// EX1: address generation shifts
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// EX2: fast load data ALUs FP operation
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// EX3: slow load data integer writeback FP operation
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// EX4: store data FP writeback
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//
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// There are shifters in both EX1 and EX2, and some instructions can be
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// flexibly allocated between them. EX2 is used as the "zero" point
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// for scheduling, so simple ALU operations executing in EX2 will have
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// ReadAdvance<0> (the default) for their source operands and Latency = 1.
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def M7UnitLoadL : ProcResource<1> { let BufferSize = 0; }
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def M7UnitLoadH : ProcResource<1> { let BufferSize = 0; }
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def M7UnitLoad : ProcResGroup<[M7UnitLoadL,M7UnitLoadH]> { let BufferSize = 0; }
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def M7UnitStore : ProcResource<1> { let BufferSize = 0; }
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def M7UnitALU : ProcResource<2>;
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def M7UnitShift1 : ProcResource<1> { let BufferSize = 0; }
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def M7UnitShift2 : ProcResource<1> { let BufferSize = 0; }
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def M7UnitMAC : ProcResource<1> { let BufferSize = 0; }
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def M7UnitBranch : ProcResource<1> { let BufferSize = 0; }
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def M7UnitVFP : ProcResource<1> { let BufferSize = 0; }
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def M7UnitVPortL : ProcResource<1> { let BufferSize = 0; }
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def M7UnitVPortH : ProcResource<1> { let BufferSize = 0; }
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def M7UnitVPort : ProcResGroup<[M7UnitVPortL,M7UnitVPortH]> { let BufferSize = 0; }
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def M7UnitSIMD : ProcResource<1> { let BufferSize = 0; }
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//===---------------------------------------------------------------------===//
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// Subtarget-specific SchedWrite types with map ProcResources and set latency.
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def : WriteRes<WriteALU, [M7UnitALU]> { let Latency = 1; }
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// Basic ALU with shifts.
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let Latency = 1 in {
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def : WriteRes<WriteALUsi, [M7UnitALU, M7UnitShift1]>;
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def : WriteRes<WriteALUsr, [M7UnitALU, M7UnitShift1]>;
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def : WriteRes<WriteALUSsr, [M7UnitALU, M7UnitShift1]>;
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}
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// Compares.
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def : WriteRes<WriteCMP, [M7UnitALU]> { let Latency = 1; }
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def : WriteRes<WriteCMPsi, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
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def : WriteRes<WriteCMPsr, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
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// Multiplies.
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let Latency = 2 in {
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def : WriteRes<WriteMUL16, [M7UnitMAC]>;
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def : WriteRes<WriteMUL32, [M7UnitMAC]>;
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def : WriteRes<WriteMUL64Lo, [M7UnitMAC]>;
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def : WriteRes<WriteMUL64Hi, []> { let NumMicroOps = 0; }
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}
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// Multiply-accumulates.
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let Latency = 2 in {
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def : WriteRes<WriteMAC16, [M7UnitMAC]>;
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def : WriteRes<WriteMAC32, [M7UnitMAC]>;
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def : WriteRes<WriteMAC64Lo, [M7UnitMAC]> { let Latency = 2; }
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def : WriteRes<WriteMAC64Hi, []> { let NumMicroOps = 0; }
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}
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// Divisions.
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// These cannot be dual-issued with any instructions.
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def : WriteRes<WriteDIV, [M7UnitALU]> {
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let Latency = 7;
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let SingleIssue = 1;
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}
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// Loads/Stores.
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def : WriteRes<WriteLd, [M7UnitLoad]> { let Latency = 1; }
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def : WriteRes<WritePreLd, [M7UnitLoad]> { let Latency = 2; }
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def : WriteRes<WriteST, [M7UnitStore]> { let Latency = 2; }
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// Branches.
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def : WriteRes<WriteBr, [M7UnitBranch]> { let Latency = 2; }
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def : WriteRes<WriteBrL, [M7UnitBranch]> { let Latency = 2; }
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def : WriteRes<WriteBrTbl, [M7UnitBranch]> { let Latency = 2; }
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// Noop.
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def : WriteRes<WriteNoop, []> { let Latency = 0; }
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//===---------------------------------------------------------------------===//
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// Sched definitions for floating-point instructions
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//
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// Floating point conversions.
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def : WriteRes<WriteFPCVT, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
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def : WriteRes<WriteFPMOV, [M7UnitVPort]> { let Latency = 3; }
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def M7WriteFPMOV64 : SchedWriteRes<[M7UnitVPortL, M7UnitVPortH]> {
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let Latency = 3;
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}
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// The FP pipeline has a latency of 3 cycles.
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// ALU operations (32/64-bit). These go down the FP pipeline.
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def : WriteRes<WriteFPALU32, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
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def : WriteRes<WriteFPALU64, [M7UnitVFP, M7UnitVPortL, M7UnitVPortH]> {
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let Latency = 4;
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let BeginGroup = 1;
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}
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// Multiplication
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def : WriteRes<WriteFPMUL32, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
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def : WriteRes<WriteFPMUL64, [M7UnitVFP, M7UnitVPortL, M7UnitVPortH]> {
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let Latency = 7;
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let BeginGroup = 1;
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}
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// Multiply-accumulate. FPMAC goes down the FP Pipeline.
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def : WriteRes<WriteFPMAC32, [M7UnitVFP, M7UnitVPort]> { let Latency = 6; }
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def : WriteRes<WriteFPMAC64, [M7UnitVFP, M7UnitVPortL, M7UnitVPortH]> {
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let Latency = 11;
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let BeginGroup = 1;
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}
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// Division. Effective scheduling latency is 3, though real latency is larger
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def : WriteRes<WriteFPDIV32, [M7UnitVFP, M7UnitVPort]> { let Latency = 16; }
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def : WriteRes<WriteFPDIV64, [M7UnitVFP, M7UnitVPortL, M7UnitVPortH]> {
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let Latency = 30;
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let BeginGroup = 1;
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}
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// Square-root. Effective scheduling latency is 3; real latency is larger
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def : WriteRes<WriteFPSQRT32, [M7UnitVFP, M7UnitVPort]> { let Latency = 16; }
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def : WriteRes<WriteFPSQRT64, [M7UnitVFP, M7UnitVPortL, M7UnitVPortH]> {
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let Latency = 30;
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let BeginGroup = 1;
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}
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def M7WriteShift2 : SchedWriteRes<[M7UnitALU, M7UnitShift2]> {}
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// Not used for M7, but needing definitions anyway
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def : WriteRes<WriteVLD1, []>;
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def : WriteRes<WriteVLD2, []>;
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def : WriteRes<WriteVLD3, []>;
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def : WriteRes<WriteVLD4, []>;
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def : WriteRes<WriteVST1, []>;
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def : WriteRes<WriteVST2, []>;
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def : WriteRes<WriteVST3, []>;
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def : WriteRes<WriteVST4, []>;
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def M7SingleIssue : SchedWriteRes<[]> {
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let SingleIssue = 1;
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let NumMicroOps = 0;
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}
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def M7Slot0Only : SchedWriteRes<[]> {
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let BeginGroup = 1;
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let NumMicroOps = 0;
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}
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// What pipeline stage operands need to be ready for depending on
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// where they come from.
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def : ReadAdvance<ReadALUsr, 0>;
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def : ReadAdvance<ReadMUL, 0>;
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def : ReadAdvance<ReadMAC, 1>;
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def : ReadAdvance<ReadALU, 0>;
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def : ReadAdvance<ReadFPMUL, 0>;
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def : ReadAdvance<ReadFPMAC, 3>;
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def M7Read_ISS : SchedReadAdvance<-1>; // operands needed at EX1
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def M7Read_EX2 : SchedReadAdvance<1>; // operands needed at EX3
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def M7Read_EX3 : SchedReadAdvance<2>; // operands needed at EX4
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// Non general purpose instructions may not be dual issued. These
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// use both issue units.
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def M7NonGeneralPurpose : SchedWriteRes<[]> {
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// Assume that these will go down the main ALU pipeline.
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// In reality, many look likely to stall the whole pipeline.
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let Latency = 3;
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let SingleIssue = 1;
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}
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// List the non general purpose instructions.
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def : InstRW<[M7NonGeneralPurpose], (instregex "t2MRS", "tSVC", "tBKPT",
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"t2MSR", "t2DMB", "t2DSB", "t2ISB",
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"t2HVC", "t2SMC", "t2UDF", "ERET",
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"tHINT", "t2HINT", "t2CLREX", "BUNDLE")>;
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//===---------------------------------------------------------------------===//
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// Sched definitions for load/store
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//
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// Mark whether the loads/stores must be single-issue
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// Address operands are needed earlier
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// Data operands are needed later
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def M7BaseUpdate : SchedWriteRes<[]> {
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let Latency = 0; // Update is bypassable out of EX1
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let NumMicroOps = 0;
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}
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def M7LoadLatency1 : SchedWriteRes<[]> {
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let Latency = 1;
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let NumMicroOps = 0;
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}
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def M7SlowLoad : SchedWriteRes<[M7UnitLoad]> { let Latency = 2; }
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// Byte and half-word loads should have greater latency than other loads.
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// So should load exclusive.
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def : InstRW<[M7SlowLoad],
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(instregex "t2LDR(B|H|SB|SH)pc")>;
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def : InstRW<[M7SlowLoad, M7Read_ISS],
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(instregex "t2LDR(B|H|SB|SH)T", "t2LDR(B|H|SB|SH)i",
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"tLDR(B|H)i")>;
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def : InstRW<[M7SlowLoad, M7Read_ISS, M7Read_ISS],
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(instregex "t2LDR(B|H|SB|SH)s", "tLDR(B|H)r", "tLDR(SB|SH)")>;
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def : InstRW<[M7SlowLoad, M7BaseUpdate, M7Read_ISS],
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(instregex "t2LDR(B|H|SB|SH)_(POST|PRE)")>;
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// Exclusive loads/stores cannot be dual-issued
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def : InstRW<[WriteLd, M7Slot0Only, M7Read_ISS],
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(instregex "t2LDREX$")>;
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def : InstRW<[M7SlowLoad, M7Slot0Only, M7Read_ISS],
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(instregex "t2LDREX(B|H)")>;
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def : InstRW<[WriteST, M7SingleIssue, M7Read_EX2, M7Read_ISS],
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(instregex "t2STREX(B|H)?$")>;
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// Load/store multiples cannot be dual-issued. Note that default scheduling
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// occurs around read/write times of individual registers in the list; read
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// time for STM cannot be overridden because it is a variadic source operand.
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def : InstRW<[WriteLd, M7SingleIssue, M7Read_ISS],
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(instregex "(t|t2)LDM(DB|IA)$")>;
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def : InstRW<[WriteST, M7SingleIssue, M7Read_ISS],
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(instregex "(t|t2)STM(DB|IA)$")>;
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def : InstRW<[M7BaseUpdate, WriteLd, M7SingleIssue, M7Read_ISS],
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(instregex "(t|t2)LDM(DB|IA)_UPD$", "tPOP")>;
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def : InstRW<[M7BaseUpdate, WriteST, M7SingleIssue, M7Read_ISS],
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(instregex "(t|t2)STM(DB|IA)_UPD$", "tPUSH")>;
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// Load/store doubles cannot be dual-issued.
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def : InstRW<[M7BaseUpdate, WriteST, M7SingleIssue,
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M7Read_EX2, M7Read_EX2, M7Read_ISS],
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(instregex "t2STRD_(PRE|POST)")>;
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def : InstRW<[WriteST, M7SingleIssue, M7Read_EX2, M7Read_EX2, M7Read_ISS],
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(instregex "t2STRDi")>;
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def : InstRW<[WriteLd, M7LoadLatency1, M7SingleIssue, M7BaseUpdate, M7Read_ISS],
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(instregex "t2LDRD_(PRE|POST)")>;
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def : InstRW<[WriteLd, M7LoadLatency1, M7SingleIssue, M7Read_ISS],
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(instregex "t2LDRDi")>;
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// Word load / preload
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def : InstRW<[WriteLd],
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(instregex "t2LDRpc", "t2PL[DI]pci", "tLDRpci")>;
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def : InstRW<[WriteLd, M7Read_ISS],
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(instregex "t2LDR(i|T)", "t2PL[DI](W)?i", "tLDRi", "tLDRspi")>;
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def : InstRW<[WriteLd, M7Read_ISS, M7Read_ISS],
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(instregex "t2LDRs", "t2PL[DI](w)?s", "tLDRr")>;
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def : InstRW<[WriteLd, M7BaseUpdate, M7Read_ISS],
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(instregex "t2LDR_(POST|PRE)")>;
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// Stores
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def : InstRW<[M7BaseUpdate, WriteST, M7Read_EX2, M7Read_ISS],
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(instregex "t2STR(B|H)?_(POST|PRE)")>;
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def : InstRW<[WriteST, M7Read_EX2, M7Read_ISS, M7Read_ISS],
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(instregex "t2STR(B|H)?s$", "tSTR(B|H)?r$")>;
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def : InstRW<[WriteST, M7Read_EX2, M7Read_ISS],
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(instregex "t2STR(B|H)?(i|T)", "tSTR(B|H)?i$", "tSTRspi")>;
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// TBB/TBH - single-issue only; takes two cycles to issue
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def M7TableLoad : SchedWriteRes<[M7UnitLoad]> {
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let NumMicroOps = 2;
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let SingleIssue = 1;
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}
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def : InstRW<[M7TableLoad, M7Read_ISS, M7Read_ISS], (instregex "t2TB")>;
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// VFP loads and stores
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def M7LoadSP : SchedWriteRes<[M7UnitLoad, M7UnitVPort]> { let Latency = 1; }
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def M7LoadDP : SchedWriteRes<[M7UnitLoadL, M7UnitLoadH, M7UnitVPortL, M7UnitVPortH]> {
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let Latency = 2;
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let SingleIssue = 1;
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}
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def M7StoreSP : SchedWriteRes<[M7UnitStore, M7UnitVPort]>;
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def M7StoreDP : SchedWriteRes<[M7UnitStore, M7UnitVPortL, M7UnitVPortH]> {
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let SingleIssue = 1;
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}
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def : InstRW<[M7LoadSP, M7Read_ISS], (instregex "VLDR(S|H)$")>;
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def : InstRW<[M7LoadDP, M7Read_ISS], (instregex "VLDRD$")>;
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def : InstRW<[M7StoreSP, M7Read_EX3, M7Read_ISS], (instregex "VSTR(S|H)$")>;
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def : InstRW<[M7StoreDP, M7Read_EX3, M7Read_ISS], (instregex "VSTRD$")>;
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// Load/store multiples cannot be dual-issued.
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def : InstRW<[WriteLd, M7SingleIssue, M7Read_ISS],
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(instregex "VLDM(S|D|Q)(DB|IA)$")>;
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def : InstRW<[WriteST, M7SingleIssue, M7Read_ISS],
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(instregex "VSTM(S|D|Q)(DB|IA)$")>;
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def : InstRW<[M7BaseUpdate, WriteLd, M7SingleIssue, M7Read_ISS],
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(instregex "VLDM(S|D|Q)(DB|IA)_UPD$")>;
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def : InstRW<[M7BaseUpdate, WriteST, M7SingleIssue, M7Read_ISS],
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(instregex "VSTM(S|D|Q)(DB|IA)_UPD$")>;
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//===---------------------------------------------------------------------===//
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// Sched definitions for ALU
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//
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// Shifted ALU operands are read a cycle early.
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def M7Ex1ReadNoFastBypass : SchedReadAdvance<-1, [WriteLd, M7LoadLatency1]>;
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def : InstRW<[WriteALUsi, M7Ex1ReadNoFastBypass, M7Read_ISS],
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(instregex "t2(ADC|ADDS|ADD|BIC|EOR|ORN|ORR|RSBS|RSB|SBC|SUBS)rs$",
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"t2(SUB|CMP|CMNz|TEQ|TST)rs$",
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"t2(A|L)SRs1$")>;
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def : InstRW<[WriteALUsi, M7Read_ISS],
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(instregex "t2MVNs")>;
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// Treat pure shift operations (except for RRX) as if they used the EX1
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// shifter but have timing as if they used the EX2 shifter as they usually
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// can choose the EX2 shifter when needed. Will miss a few dual-issue cases,
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// but the results prove to be better than trying to get them exact.
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def : InstRW<[M7WriteShift2, M7Read_ISS], (instregex "t2RRX$")>;
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def : InstRW<[WriteALUsi], (instregex "(t|t2)(LSL|LSR|ASR|ROR)r", "tROR")>;
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// Instructions that use the shifter, but have normal timing.
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def : InstRW<[WriteALUsi,M7Slot0Only], (instregex "t2(BFC|BFI)$")>;
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// Instructions which are slot zero only but otherwise normal.
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def : InstRW<[WriteALU, M7Slot0Only], (instregex "t2CLZ")>;
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// MAC operations that don't have SchedRW set.
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def : InstRW<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC], (instregex "t2SML[AS]D")>;
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// Divides are special because they stall for their latency, and so look like a
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// single-cycle as far as scheduling opportunities go. By putting WriteALU
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// first, we make the operand latency 1, but keep the instruction latency 7.
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def : InstRW<[WriteALU, WriteDIV], (instregex "t2(S|U)DIV")>;
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// DSP extension operations
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def M7WriteSIMD1 : SchedWriteRes<[M7UnitSIMD, M7UnitALU]> {
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let Latency = 1;
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let BeginGroup = 1;
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}
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def M7WriteSIMD2 : SchedWriteRes<[M7UnitSIMD, M7UnitALU]> {
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let Latency = 2;
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let BeginGroup = 1;
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}
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def M7WriteShSIMD1 : SchedWriteRes<[M7UnitSIMD, M7UnitALU, M7UnitShift1]> {
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let Latency = 1;
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let BeginGroup = 1;
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}
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def M7WriteShSIMD0 : SchedWriteRes<[M7UnitSIMD, M7UnitALU, M7UnitShift1]> {
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let Latency = 0; // Bypassable out of EX1
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let BeginGroup = 1;
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}
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def M7WriteShSIMD2 : SchedWriteRes<[M7UnitSIMD, M7UnitALU, M7UnitShift1]> {
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let Latency = 2;
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let BeginGroup = 1;
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}
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def : InstRW<[M7WriteShSIMD2, M7Read_ISS],
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(instregex "t2(S|U)SAT")>;
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def : InstRW<[M7WriteSIMD1, ReadALU],
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(instregex "(t|t2)(S|U)XT(B|H)")>;
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def : InstRW<[M7WriteSIMD1, ReadALU, ReadALU],
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(instregex "t2(S|SH|U|UH)(ADD16|ADD8|ASX|SAX|SUB16|SUB8)",
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|
"t2SEL")>;
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def : InstRW<[M7WriteSIMD2, ReadALU, ReadALU],
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(instregex "t2(Q|UQ)(ADD|ASX|SAX|SUB)", "t2USAD8")>;
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def : InstRW<[M7WriteShSIMD2, M7Read_ISS, M7Read_ISS],
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(instregex "t2QD(ADD|SUB)")>;
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def : InstRW<[M7WriteShSIMD0, M7Read_ISS],
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|
(instregex "t2(RBIT|REV)", "tREV")>;
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def : InstRW<[M7WriteShSIMD1, M7Read_ISS],
|
|
(instregex "t2(SBFX|UBFX)")>;
|
|
def : InstRW<[M7WriteShSIMD1, ReadALU, M7Read_ISS],
|
|
(instregex "t2PKH(BT|TB)", "t2(S|U)XTA")>;
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def : InstRW<[M7WriteSIMD2, ReadALU, ReadALU, M7Read_EX2],
|
|
(instregex "t2USADA8")>;
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|
|
|
// MSR/MRS
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def : InstRW<[M7NonGeneralPurpose], (instregex "MSR", "MRS")>;
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|
|
|
//===---------------------------------------------------------------------===//
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|
// Sched definitions for FP operations
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|
//
|
|
|
|
// Effective scheduling latency is really 3 for nearly all FP operations,
|
|
// even if their true latency is higher.
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|
def M7WriteVFPLatOverride : SchedWriteRes<[]> {
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|
let Latency = 3;
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|
let NumMicroOps = 0;
|
|
}
|
|
def M7WriteVFPExtraVPort : SchedWriteRes<[M7UnitVPort]> {
|
|
let Latency = 3;
|
|
let NumMicroOps = 0;
|
|
}
|
|
|
|
// Instructions which are missing default schedules.
|
|
def : InstRW<[WriteFPALU32],
|
|
(instregex "V(ABS|CVT.*|NEG|FP_VMAX.*|FP_VMIN.*|RINT.*)S$")>;
|
|
def : InstRW<[M7WriteVFPLatOverride, WriteFPALU64],
|
|
(instregex "V(ABS|CVT.*|NEG|FP_VMAX.*|FP_VMIN.*|RINT.*)D$")>;
|
|
|
|
// VCMP
|
|
def M7WriteVCMPS : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let Latency = 0; }
|
|
def M7WriteVCMPD : SchedWriteRes<[M7UnitVFP, M7UnitVPort, M7UnitVPort]> {
|
|
let Latency = 0;
|
|
let BeginGroup = 1;
|
|
}
|
|
def : InstRW<[M7WriteVCMPS], (instregex "VCMPS$")>;
|
|
def : InstRW<[M7WriteVCMPD], (instregex "VCMPD$")>;
|
|
|
|
// VMRS/VMSR
|
|
def M7VMRS : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let SingleIssue = 1; }
|
|
def M7VMSR : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let SingleIssue = 1; }
|
|
def : InstRW<[M7VMRS], (instregex "FMSTAT")>;
|
|
def : InstRW<[M7VMSR], (instregex "VMSR")>;
|
|
|
|
// VSEL cannot bypass in its implied $cpsr operand; model as earlier read
|
|
def : InstRW<[WriteFPALU32, M7Slot0Only, ReadALU, ReadALU, M7Read_ISS],
|
|
(instregex "VSEL.*S$")>;
|
|
def : InstRW<[M7WriteVFPLatOverride, WriteFPALU64, M7Slot0Only,
|
|
ReadALU, ReadALU, M7Read_ISS],
|
|
(instregex "VSEL.*D$")>;
|
|
|
|
// VMOV
|
|
def : InstRW<[WriteFPMOV],
|
|
(instregex "VMOV(H|S)$", "FCONST(H|S)")>;
|
|
def : InstRW<[WriteFPMOV, M7WriteVFPExtraVPort, M7Slot0Only],
|
|
(instregex "VMOVD$")>;
|
|
def : InstRW<[WriteFPMOV, M7WriteVFPExtraVPort, M7Slot0Only],
|
|
(instregex "FCONSTD")>;
|
|
def : InstRW<[WriteFPMOV, M7WriteVFPExtraVPort, M7SingleIssue],
|
|
(instregex "VMOV(DRR|RRD|RRS|SRR)")>;
|
|
|
|
// Larger-latency overrides.
|
|
|
|
def : InstRW<[M7WriteVFPLatOverride, WriteFPDIV32], (instregex "VDIVS")>;
|
|
def : InstRW<[M7WriteVFPLatOverride, WriteFPDIV64], (instregex "VDIVD")>;
|
|
def : InstRW<[M7WriteVFPLatOverride, WriteFPSQRT32], (instregex "VSQRTS")>;
|
|
def : InstRW<[M7WriteVFPLatOverride, WriteFPSQRT64], (instregex "VSQRTD")>;
|
|
def : InstRW<[M7WriteVFPLatOverride, WriteFPMUL64],
|
|
(instregex "V(MUL|NMUL)D")>;
|
|
def : InstRW<[M7WriteVFPLatOverride, WriteFPALU64],
|
|
(instregex "V(ADD|SUB)D")>;
|
|
|
|
// Multiply-accumulate. Chained SP timing is correct; rest need overrides
|
|
// Double-precision chained MAC stalls the pipeline behind it for 3 cycles,
|
|
// making it appear to have 3 cycle latency for scheduling.
|
|
|
|
def : InstRW<[M7WriteVFPLatOverride, WriteFPMAC64,
|
|
ReadFPMAC, ReadFPMUL, ReadFPMUL],
|
|
(instregex "V(N)?ML(A|S)D$")>;
|
|
|
|
// Single-precision fused MACs look like latency 5 with advance of 2.
|
|
|
|
def M7WriteVFPLatOverride5 : SchedWriteRes<[]> {
|
|
let Latency = 5;
|
|
let NumMicroOps = 0;
|
|
}
|
|
def M7ReadFPMAC2 : SchedReadAdvance<2>;
|
|
|
|
def : InstRW<[M7WriteVFPLatOverride5, WriteFPMAC32,
|
|
M7ReadFPMAC2, ReadFPMUL, ReadFPMUL],
|
|
(instregex "VF(N)?M(A|S)S$")>;
|
|
|
|
// Double-precision fused MAC stalls the pipeline behind it for 2 cycles, making
|
|
// it appear to have 3 cycle latency for scheduling.
|
|
|
|
def : InstRW<[M7WriteVFPLatOverride, WriteFPMAC64,
|
|
ReadFPMAC, ReadFPMUL, ReadFPMUL],
|
|
(instregex "VF(N)?M(A|S)D$")>;
|
|
|
|
} // SchedModel = CortexM7Model
|