26fdad031c
This is a follow-on to https://reviews.llvm.org/D134073. The number of MIPS16 changes here is a bit surprising. Many of the fields with mismatched names were NOT previously choosing the correct argument positionally, but instead doing something completely wrong (e.g. it would encode a register where an immediate was expected). But, machine-code generation for MIPS16 has never actually functioned. It's also fully untested, thus, the MIPS16 changes, despite changing behavior, breaks (and fixes) zero tests. This change does not fix MIPS16 output, but it ought to be at least incrementally less broken. Outside MIPS16, I believe the only functional change is to the 'ginvi' instruction: it was previously encoding garbage into a field which was specified to be '00'. Fortunately, it was covered by tests -- and the tests were testing the incorrect behavior. So, fixed. Differential Revision: https://reviews.llvm.org/D134220
84 lines
2.5 KiB
TableGen
84 lines
2.5 KiB
TableGen
//===- MipsEVAInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips32r6 instruction formats.
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//
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//===----------------------------------------------------------------------===//
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class MipsEVAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
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StdArch {
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let DecoderNamespace = "Mips";
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let EncodingPredicates = [HasStdEnc];
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}
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//===----------------------------------------------------------------------===//
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//
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// Field Values
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//
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//===----------------------------------------------------------------------===//
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// Memory Load/Store EVA
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def OPCODE6_LBE : OPCODE6<0b101100>;
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def OPCODE6_LBuE : OPCODE6<0b101000>;
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def OPCODE6_LHE : OPCODE6<0b101101>;
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def OPCODE6_LHuE : OPCODE6<0b101001>;
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def OPCODE6_LWE : OPCODE6<0b101111>;
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def OPCODE6_SBE : OPCODE6<0b011100>;
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def OPCODE6_SHE : OPCODE6<0b011101>;
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def OPCODE6_SWE : OPCODE6<0b011111>;
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// load/store left/right EVA
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def OPCODE6_LWLE : OPCODE6<0b011001>;
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def OPCODE6_LWRE : OPCODE6<0b011010>;
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def OPCODE6_SWLE : OPCODE6<0b100001>;
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def OPCODE6_SWRE : OPCODE6<0b100010>;
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// Load-linked EVA, Store-conditional EVA
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def OPCODE6_LLE : OPCODE6<0b101110>;
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def OPCODE6_SCE : OPCODE6<0b011110>;
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def OPCODE6_TLBINV : OPCODE6<0b000011>;
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def OPCODE6_TLBINVF : OPCODE6<0b000100>;
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def OPCODE6_CACHEE : OPCODE6<0b011011>;
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def OPCODE6_PREFE : OPCODE6<0b100011>;
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def OPGROUP_COP0_TLB : OPGROUP<0b010000>;
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//===----------------------------------------------------------------------===//
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//
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// Encoding Formats
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//
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//===----------------------------------------------------------------------===//
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class SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6 Operation> : MipsEVAInst {
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bits<21> addr;
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bits<5> rt;
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bits<5> base = addr{20-16};
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bits<9> offset = addr{8-0};
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_SPECIAL3.Value;
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let Inst{25-21} = base;
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let Inst{20-16} = rt;
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let Inst{15-7} = offset;
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let Inst{6} = 0;
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let Inst{5-0} = Operation.Value;
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}
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class TLB_FM<OPCODE6 Operation> : MipsEVAInst {
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bits<32> Inst;
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let Inst{31-26} = OPGROUP_COP0_TLB.Value;
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let Inst{25} = 1; // CO
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let Inst{24-6} = 0;
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let Inst{5-0} = Operation.Value;
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}
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