5e5fd0e6fc
SM80 has fma for bfloat16 but not add/mul/sub. Currently these ops incur a promotion to f32, but we can avoid this by writing them in terms of the fma: ``` FADD(a, b) -> FMA(a, 1.0, b) FMUL(a, b) -> FMA(a, b, -0.0) FSUB(a, b) -> FMA(b, -1.0, a) ``` Unfortunately there is no `fma.ftz` so when ftz is enabled, we still fall back to promotion.
115 lines
3.5 KiB
C++
115 lines
3.5 KiB
C++
//===- NVPTXSubtarget.cpp - NVPTX Subtarget Information -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the NVPTX specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTXSubtarget.h"
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#include "NVPTXSelectionDAGInfo.h"
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#include "NVPTXTargetMachine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormatVariadic.h"
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using namespace llvm;
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#define DEBUG_TYPE "nvptx-subtarget"
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#define GET_SUBTARGETINFO_ENUM
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "NVPTXGenSubtargetInfo.inc"
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static cl::opt<bool>
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NoF16Math("nvptx-no-f16-math", cl::Hidden,
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cl::desc("NVPTX Specific: Disable generation of f16 math ops."),
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cl::init(false));
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// Pin the vtable to this file.
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void NVPTXSubtarget::anchor() {}
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NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
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StringRef FS) {
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TargetName = std::string(CPU);
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ParseSubtargetFeatures(getTargetName(), /*TuneCPU=*/getTargetName(), FS);
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// Re-map SM version numbers, SmVersion carries the regular SMs which do
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// have relative order, while FullSmVersion allows distinguishing sm_90 from
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// sm_90a, which would *not* be a subset of sm_91.
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SmVersion = getSmVersion();
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// Set default to PTX 6.0 (CUDA 9.0)
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if (PTXVersion == 0) {
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PTXVersion = 60;
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}
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return *this;
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}
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NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS,
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const NVPTXTargetMachine &TM)
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: NVPTXGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), PTXVersion(0),
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FullSmVersion(200), SmVersion(getSmVersion()),
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TLInfo(TM, initializeSubtargetDependencies(CPU, FS)) {
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TSInfo = std::make_unique<NVPTXSelectionDAGInfo>();
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}
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NVPTXSubtarget::~NVPTXSubtarget() = default;
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const SelectionDAGTargetInfo *NVPTXSubtarget::getSelectionDAGInfo() const {
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return TSInfo.get();
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}
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bool NVPTXSubtarget::allowFP16Math() const {
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return hasFP16Math() && NoF16Math == false;
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}
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bool NVPTXSubtarget::hasNativeBF16Support(int Opcode) const {
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if (!hasBF16Math())
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return false;
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switch (Opcode) {
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// Several BF16 instructions are available on sm_90 only.
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case ISD::FADD:
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case ISD::FMUL:
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case ISD::FSUB:
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case ISD::SELECT:
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case ISD::SELECT_CC:
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case ISD::SETCC:
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case ISD::FEXP2:
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case ISD::FCEIL:
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case ISD::FFLOOR:
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case ISD::FNEARBYINT:
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case ISD::FRINT:
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case ISD::FROUNDEVEN:
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case ISD::FTRUNC:
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return getSmVersion() >= 90 && getPTXVersion() >= 78;
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// Several BF16 instructions are available on sm_80 only.
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case ISD::FMINNUM:
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case ISD::FMAXNUM:
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case ISD::FMAXNUM_IEEE:
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case ISD::FMINNUM_IEEE:
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case ISD::FMAXIMUM:
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case ISD::FMINIMUM:
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return getSmVersion() >= 80 && getPTXVersion() >= 70;
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}
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return true;
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}
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void NVPTXSubtarget::failIfClustersUnsupported(
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std::string const &FailureMessage) const {
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if (hasClusters())
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return;
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report_fatal_error(formatv(
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"NVPTX SM architecture \"{}\" and PTX version \"{}\" do not support {}. "
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"Requires SM >= 90 and PTX >= 78.",
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getFullSmVersion(), PTXVersion, FailureMessage));
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}
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