c60db55568
This commit moves RISC-V to auto-generate its target-specific SDNode types. The biggest change is that SDNodes can now be validated against their expected type profiles, and that we don't need to edit several different files when declaring a new one. This takes Sergei's work in #119709 and "finishes" it - by moving the final five RISCVISD opcodes into tablegen (including defining their types), and by ensuring the tablegen has expected closing scope comments. Co-authored-by: Sergei Barannikov <barannikov88@gmail.com>
53 lines
2.5 KiB
TableGen
53 lines
2.5 KiB
TableGen
//===-- RISCVInstrInfoZicond.td ----------------------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard Integer
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// Conditional operations extension (Zicond).
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// RISC-V specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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// Branchless select operations, matching the semantics of the instructions
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// defined in Zicond or XVentanaCondOps
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def riscv_czero_eqz : RVSDNode<"CZERO_EQZ", SDTIntBinOp>; // vt.maskc for XVentanaCondOps.
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def riscv_czero_nez : RVSDNode<"CZERO_NEZ", SDTIntBinOp>; // vt.maskcn for XVentanaCondOps.
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZicond] in {
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def CZERO_EQZ : ALU_rr<0b0000111, 0b101, "czero.eqz">,
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Sched<[WriteIALU, ReadIALU, ReadIALU]>;
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def CZERO_NEZ : ALU_rr<0b0000111, 0b111, "czero.nez">,
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Sched<[WriteIALU, ReadIALU, ReadIALU]>;
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} // Predicates = [HasStdExtZicond]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZicond] in {
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def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
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(CZERO_EQZ GPR:$rs1, GPR:$rc)>;
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def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, GPR:$rc)),
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(CZERO_NEZ GPR:$rs1, GPR:$rc)>;
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def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
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(CZERO_EQZ GPR:$rs1, GPR:$rc)>;
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def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
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(CZERO_NEZ GPR:$rs1, GPR:$rc)>;
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def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
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(CZERO_NEZ GPR:$rs1, GPR:$rc)>;
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def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
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(CZERO_EQZ GPR:$rs1, GPR:$rc)>;
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} // Predicates = [HasStdExtZicond]
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