c2a818f48b
XSfvqmaccdod/qoq and XSfvfwmaccqqq are SiFive's small-size matrix multiplication extensions. This patches add scheduling info for their instructions along with six new SchedReadWrite.
102 lines
3.5 KiB
TableGen
102 lines
3.5 KiB
TableGen
//===-- RISCVScheduleXSf.td - Scheduling Definitions XSf ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the scheduling information for SiFive extensions.
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//
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//===----------------------------------------------------------------------===//
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multiclass LMULSchedWritesVCIX<string id>{
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defm "" : LMULSchedWrites<"WriteVC_" # id>;
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defm "" : LMULSchedWrites<"WriteVC_V_" # id>;
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}
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defm "" : LMULSchedWritesVCIX<"I">;
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defm "" : LMULSchedWritesVCIX<"X">;
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defm "" : LMULSchedWritesVCIX<"IV">;
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defm "" : LMULSchedWritesVCIX<"VV">;
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defm "" : LMULSchedWritesVCIX<"XV">;
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defm "" : LMULSchedWritesVCIX<"IVV">;
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defm "" : LMULSchedWritesVCIX<"IVW">;
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defm "" : LMULSchedWritesVCIX<"VVV">;
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defm "" : LMULSchedWritesVCIX<"VVW">;
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defm "" : LMULSchedWritesVCIX<"XVV">;
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defm "" : LMULSchedWritesVCIX<"XVW">;
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foreach f = ["FPR16", "FPR32", "FPR64"] in {
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defm "" : LMULSchedWritesVCIX<f # "V">;
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defm "" : LMULSchedWritesVCIX<f # "VV">;
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defm "" : LMULSchedWritesVCIX<f # "VW">;
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}
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multiclass LMULWriteResVCIX<string id, list<ProcResourceKind> resources>{
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defm : LMULWriteRes<"WriteVC_" # id, resources>;
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defm : LMULWriteRes<"WriteVC_V_" # id, resources>;
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}
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multiclass UnsupportedSchedXsfvcp {
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let Unsupported = true in {
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defm : LMULWriteResVCIX<"I", []>;
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defm : LMULWriteResVCIX<"X", []>;
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defm : LMULWriteResVCIX<"IV", []>;
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defm : LMULWriteResVCIX<"VV", []>;
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defm : LMULWriteResVCIX<"XV", []>;
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defm : LMULWriteResVCIX<"IVV", []>;
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defm : LMULWriteResVCIX<"IVW", []>;
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defm : LMULWriteResVCIX<"VVV", []>;
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defm : LMULWriteResVCIX<"VVW", []>;
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defm : LMULWriteResVCIX<"XVV", []>;
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defm : LMULWriteResVCIX<"XVW", []>;
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foreach f = ["FPR16", "FPR32", "FPR64"] in {
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defm : LMULWriteResVCIX<f # "V", []>;
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defm : LMULWriteResVCIX<f # "VV", []>;
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defm : LMULWriteResVCIX<f # "VW", []>;
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}
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}
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}
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defm "" : LMULSchedWritesImpl<"WriteSF_VFNRClipV", !listremove(SchedMxListW, ["M4"])>;
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defm "" : LMULSchedReadsImpl<"ReadSF_VFNRClipV", !listremove(SchedMxListW, ["M4"])>;
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defm "" : LMULSchedReadsImpl<"ReadSF_VFNRClipF", !listremove(SchedMxListW, ["M4"])>;
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multiclass UnsupportedSchedXSfvfnrclipxfqf {
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let Unsupported = true in {
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defm : LMULWriteRes<"WriteSF_VFNRClipV", []>;
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defm : LMULReadAdvance<"ReadSF_VFNRClipV", 0>;
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defm : LMULReadAdvance<"ReadSF_VFNRClipF", 0>;
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} // Unsupported = true
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}
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defm "" : LMULSchedWritesImpl<"WriteSF_VQMACC_DOD", ["M1", "M2", "M4", "M8"]>;
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defm "" : LMULSchedReadsImpl<"ReadSF_VQMACC_DOD", ["M1", "M2", "M4", "M8"]>;
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multiclass UnsupportedSchedXSfvqmaccdod {
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let Unsupported = true in {
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defm : LMULWriteRes<"WriteSF_VQMACC_DOD", []>;
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defm : LMULReadAdvance<"ReadSF_VQMACC_DOD", 0>;
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} // Unsupported = true
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}
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defm "" : LMULSchedWritesImpl<"WriteSF_VQMACC_QOQ", ["MF2", "M1", "M2", "M4"]>;
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defm "" : LMULSchedReadsImpl<"ReadSF_VQMACC_QOQ", ["MF2", "M1", "M2", "M4"]>;
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multiclass UnsupportedSchedXSfvqmaccqoq {
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let Unsupported = true in {
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defm : LMULWriteRes<"WriteSF_VQMACC_QOQ", []>;
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defm : LMULReadAdvance<"ReadSF_VQMACC_QOQ", 0>;
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} // Unsupported = true
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}
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defm "" : LMULSchedWritesImpl<"WriteSF_VFWMACC_QQQ", SchedMxListFW>;
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defm "" : LMULSchedReadsImpl<"ReadSF_VFWMACC_QQQ", SchedMxListFW>;
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multiclass UnsupportedSchedXSfvfwmaccqqq {
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let Unsupported = true in {
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defm : LMULWriteRes<"WriteSF_VFWMACC_QQQ", []>;
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defm : LMULReadAdvance<"ReadSF_VFWMACC_QQQ", 0>;
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} // Unsupported = true
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}
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