c9684e5892
This patch adds support for converting memset calls to one or more `QC_SETWMI` instructions when beneficial. We only handle aligned memset calls for now. We limit a `QC_SETWMI` to 16 words or less to improve interruptibility. So for `1-16` words we use a single `QC_SETWMI`: `QC_SETWMI reg1, N, 0(reg2)` For `17-32 `words we use two `QC_SETWMI's` with the first as 16 words and the second for the remainder: ``` QC_SETWMI reg1, 16, 0(reg2) QC_SETWMI reg1, N, 64(reg2) ``` For `33-48` words, we would like to use `(16, 16, n)`, but that means the last QC_SETWMI needs an offset of `128` which the instruction doesn't support. So in this case we use a length of `15` for the second instruction and we do the rest with the third instruction. This means the maximum number of words handled is `47` (for now): ``` QC_SETWMI R2, R0, 16, 0 QC_SETWMI R2, R0, 15, 64 QC_SETWMI R2, R0, N, 124 ``` For `48` words or more, call the target independent memset.
68 lines
2.1 KiB
C++
68 lines
2.1 KiB
C++
//===----------------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVSELECTIONDAGINFO_H
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#define LLVM_LIB_TARGET_RISCV_RISCVSELECTIONDAGINFO_H
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#include "llvm/CodeGen/SDNodeInfo.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#define GET_SDNODE_ENUM
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#include "RISCVGenSDNodeInfo.inc"
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namespace llvm {
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namespace RISCVISD {
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// RISCVISD Node TSFlags
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enum : llvm::SDNodeTSFlags {
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HasPassthruOpMask = 1 << 0,
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HasMaskOpMask = 1 << 1,
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};
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} // namespace RISCVISD
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class RISCVSelectionDAGInfo : public SelectionDAGGenTargetInfo {
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public:
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RISCVSelectionDAGInfo();
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~RISCVSelectionDAGInfo() override;
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void verifyTargetNode(const SelectionDAG &DAG,
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const SDNode *N) const override;
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SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl,
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SDValue Chain, SDValue Dst, SDValue Src,
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SDValue Size, Align Alignment,
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bool isVolatile, bool AlwaysInline,
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MachinePointerInfo DstPtrInfo) const override;
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bool hasPassthruOp(unsigned Opcode) const {
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return GenNodeInfo.getDesc(Opcode).TSFlags & RISCVISD::HasPassthruOpMask;
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}
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bool hasMaskOp(unsigned Opcode) const {
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return GenNodeInfo.getDesc(Opcode).TSFlags & RISCVISD::HasMaskOpMask;
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}
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unsigned getMAccOpcode(unsigned MulOpcode) const {
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switch (static_cast<RISCVISD::GenNodeType>(MulOpcode)) {
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default:
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llvm_unreachable("Unexpected opcode");
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case RISCVISD::VWMUL_VL:
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return RISCVISD::VWMACC_VL;
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case RISCVISD::VWMULU_VL:
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return RISCVISD::VWMACCU_VL;
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case RISCVISD::VWMULSU_VL:
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return RISCVISD::VWMACCSU_VL;
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}
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}
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};
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_RISCV_RISCVSELECTIONDAGINFO_H
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