81 lines
3.5 KiB
TableGen
81 lines
3.5 KiB
TableGen
//=== SparcInstrUAOSA.td - UltraSPARC/Oracle SPARC Architecture extensions ===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains instruction formats, definitions and patterns needed for
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// UA 2005, UA 2007, and OSA 2011 instructions on SPARC.
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//===----------------------------------------------------------------------===//
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class UA2005RegWin<string asmstr, bits<5> fcn>
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: F3_1<2, 0b110001, (outs), (ins), asmstr, []> {
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let rd = fcn;
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let rs1 = 0;
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let rs2 = 0;
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}
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// Convenience template for 4-operand instructions
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class FourOp<string OpcStr, bits<6> op3val, bits<4> op5val,
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RegisterClass RC>
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: F3_4<op3val, op5val, (outs RC:$rd), (ins RC:$rs1, RC:$rs2, RC:$rs3),
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!strconcat(OpcStr, " $rs1, $rs2, $rs3, $rd")>;
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/// F2_56 multiclass - Define a F2_5/F2_6 pattern in one shot.
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multiclass F2_56<string OpcStr, bits<1> cc> {
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def rr : F2_5<cc, (outs),
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(ins cbtarget:$imm10, CCOp:$cond, IntRegs:$rs1, IntRegs:$rs2),
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!strconcat(OpcStr, "$cond $rs1, $rs2, $imm10")>;
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def ri : F2_6<cc, (outs),
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(ins cbtarget:$imm10, CCOp:$cond, IntRegs:$rs1, simm5Op:$simm5),
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!strconcat(OpcStr, "$cond $rs1, $simm5, $imm10")>;
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}
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// UltraSPARC Architecture 2005 Instructions
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let Predicates = [HasUA2005] in {
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let hasSideEffects = 1 in {
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def ALLCLEAN : UA2005RegWin<"allclean", 0b00010>;
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def INVALW : UA2005RegWin<"invalw", 0b00101>;
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def NORMALW : UA2005RegWin<"normalw", 0b00100>;
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def OTHERW : UA2005RegWin<"otherw", 0b00011>;
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}
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} // Predicates = [HasUA2005]
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// UltraSPARC Architecture 2007 Instructions
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let Predicates = [HasUA2007] in {
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def FMADDS : FourOp<"fmadds", 0b110111, 0b0001, FPRegs>;
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def FMADDD : FourOp<"fmaddd", 0b110111, 0b0010, DFPRegs>;
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def FMSUBS : FourOp<"fmsubs", 0b110111, 0b0101, FPRegs>;
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def FMSUBD : FourOp<"fmsubd", 0b110111, 0b0110, DFPRegs>;
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def FNMADDS : FourOp<"fnmadds", 0b110111, 0b1101, FPRegs>;
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def FNMADDD : FourOp<"fnmaddd", 0b110111, 0b1110, DFPRegs>;
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def FNMSUBS : FourOp<"fnmsubs", 0b110111, 0b1001, FPRegs>;
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def FNMSUBD : FourOp<"fnmsubd", 0b110111, 0b1010, DFPRegs>;
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} // Predicates = [HasUA2007]
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// Oracle SPARC Architecture 2011 Instructions
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let Predicates = [HasOSA2011] in {
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let isBranch = 1, isTerminator = 1, hasDelaySlot = 0 in {
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defm CWBCOND : F2_56<"cwb", 0>;
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defm CXBCOND : F2_56<"cxb", 1>;
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}
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def FPMADDX : FourOp<"fpmaddx", 0b110111, 0b0000, DFPRegs>;
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def FPMADDXHI : FourOp<"fpmaddxhi", 0b110111, 0b0100, DFPRegs>;
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} // Predicates = [HasOSA2011]
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// UA2007 instruction patterns.
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let Predicates = [HasUA2007] in {
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def : Pat<(f32 (any_fma f32:$rs1, f32:$rs2, f32:$add)), (FMADDS $rs1, $rs2, $add)>;
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def : Pat<(f64 (any_fma f64:$rs1, f64:$rs2, f64:$add)), (FMADDD $rs1, $rs2, $add)>;
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def : Pat<(f32 (any_fma f32:$rs1, f32:$rs2, (fneg f32:$sub))), (FMSUBS $rs1, $rs2, $sub)>;
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def : Pat<(f64 (any_fma f64:$rs1, f64:$rs2, (fneg f64:$sub))), (FMSUBD $rs1, $rs2, $sub)>;
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def : Pat<(f32 (fneg (any_fma f32:$rs1, f32:$rs2, f32:$add))), (FNMADDS $rs1, $rs2, $add)>;
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def : Pat<(f64 (fneg (any_fma f64:$rs1, f64:$rs2, f64:$add))), (FNMADDD $rs1, $rs2, $add)>;
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def : Pat<(f32 (fneg (any_fma f32:$rs1, f32:$rs2, (fneg f32:$sub)))), (FNMSUBS $rs1, $rs2, $sub)>;
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def : Pat<(f64 (fneg (any_fma f64:$rs1, f64:$rs2, (fneg f64:$sub)))), (FNMSUBD $rs1, $rs2, $sub)>;
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} // Predicates = [HasUA2007]
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