3f15b66dec
Reviewers: brad0, s-barannikov, arsenm, rorth Reviewed By: arsenm Pull Request: https://github.com/llvm/llvm-project/pull/135718
353 lines
15 KiB
TableGen
353 lines
15 KiB
TableGen
//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains instruction formats, definitions and patterns needed for
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// VIS, VIS II, VIS III instructions on SPARC.
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//===----------------------------------------------------------------------===//
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// VIS Instruction Format.
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class VISInstFormat<bits<9> opfval, dag outs, dag ins, string asmstr>
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: F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, []>;
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class VISInst<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
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: VISInstFormat<opfval,
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(outs RC:$rd), (ins RC:$rs1, RC:$rs2),
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!strconcat(OpcStr, " $rs1, $rs2, $rd")>;
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// VIS Instruction with integer destination register.
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class VISInstID<bits<9> opfval, string OpcStr>
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: VISInstFormat<opfval,
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(outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
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!strconcat(OpcStr, " $rs1, $rs2, $rd")>;
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// For VIS Instructions with no operand.
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let rd = 0, rs1 = 0, rs2 = 0 in
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class VISInst0<bits<9> opfval, string asmstr>
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: VISInstFormat<opfval, (outs), (ins), asmstr>;
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// For VIS Instructions with only rs1, rd operands.
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let rs2 = 0 in
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class VISInst1<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
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: VISInstFormat<opfval,
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(outs RC:$rd), (ins RC:$rs1),
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!strconcat(OpcStr, " $rs1, $rd")>;
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// For VIS Instructions with only rs2, rd operands.
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let rs1 = 0 in
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class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
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: VISInstFormat<opfval,
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(outs RC:$rd), (ins RC:$rs2),
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!strconcat(OpcStr, " $rs2, $rd")>;
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// For VIS Instructions with only rd operand.
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let rs1 = 0, rs2 = 0 in
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class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
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: VISInstFormat<opfval,
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(outs RC:$rd), (ins),
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!strconcat(OpcStr, " $rd")>;
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// VIS 1 Instructions
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let Predicates = [HasVIS] in {
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def FPADD16 : VISInst<0b001010000, "fpadd16">;
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def FPADD16S : VISInst<0b001010001, "fpadd16s", FPRegs>;
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def FPADD32 : VISInst<0b001010010, "fpadd32">;
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def FPADD32S : VISInst<0b001010011, "fpadd32s", FPRegs>;
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def FPSUB16 : VISInst<0b001010100, "fpsub16">;
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def FPSUB16S : VISInst<0b001010101, "fpsub16s", FPRegs>;
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def FPSUB32 : VISInst<0b001010110, "fpsub32">;
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def FPSUB32S : VISInst<0b001010111, "fpsub32s", FPRegs>;
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def FPACK16 : VISInst2<0b000111011, "fpack16">;
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def FPACK32 : VISInst <0b000111010, "fpack32">;
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let rs1 = 0 in
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def FPACKFIX : VISInstFormat<0b000111101,
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(outs FPRegs:$rd), (ins DFPRegs:$rs2), "fpackfix $rs2, $rd">;
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let rs1 = 0 in
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def FEXPAND : VISInstFormat<0b001001101,
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(outs DFPRegs:$rd), (ins FPRegs:$rs2), "fexpand $rs2, $rd">;
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def FPMERGE : VISInstFormat<0b001001011,
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(outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fpmerge $rs1, $rs2, $rd">;
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def FMUL8X16 : VISInstFormat<0b000110001,
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(outs DFPRegs:$rd), (ins FPRegs:$rs1, DFPRegs:$rs2),
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"fmul8x16 $rs1, $rs2, $rd">;
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def FMUL8X16AU : VISInstFormat<0b000110011,
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(outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fmul8x16au $rs1, $rs2, $rd">;
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def FMUL8X16AL : VISInstFormat<0b000110101,
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(outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fmul8x16al $rs1, $rs2, $rd">;
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def FMUL8SUX16 : VISInst<0b000110110, "fmul8sux16">;
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def FMUL8ULX16 : VISInst<0b000110111, "fmul8ulx16">;
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def FMULD8SUX16 : VISInstFormat<0b000111000,
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(outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fmuld8sux16 $rs1, $rs2, $rd">;
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def FMULD8ULX16 : VISInstFormat<0b000111001,
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(outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fmuld8ulx16 $rs1, $rs2, $rd">;
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def ALIGNADDR : VISInst<0b000011000, "alignaddr", I64Regs>;
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def ALIGNADDRL : VISInst<0b000011010, "alignaddrl", I64Regs>;
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def FALIGNADATA : VISInst<0b001001000, "faligndata">;
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def FZERO : VISInstD<0b001100000, "fzero">;
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def FZEROS : VISInstD<0b001100001, "fzeros", FPRegs>;
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def FONE : VISInstD<0b001111110, "fone">;
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def FONES : VISInstD<0b001111111, "fones", FPRegs>;
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def FSRC1 : VISInst1<0b001110100, "fsrc1">;
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def FSRC1S : VISInst1<0b001110101, "fsrc1s", FPRegs>;
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def FSRC2 : VISInst2<0b001111000, "fsrc2">;
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def FSRC2S : VISInst2<0b001111001, "fsrc2s", FPRegs>;
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def FNOT1 : VISInst1<0b001101010, "fnot1">;
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def FNOT1S : VISInst1<0b001101011, "fnot1s", FPRegs>;
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def FNOT2 : VISInst2<0b001100110, "fnot2">;
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def FNOT2S : VISInst2<0b001100111, "fnot2s", FPRegs>;
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def FOR : VISInst<0b001111100, "for">;
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def FORS : VISInst<0b001111101, "fors", FPRegs>;
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def FNOR : VISInst<0b001100010, "fnor">;
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def FNORS : VISInst<0b001100011, "fnors", FPRegs>;
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def FAND : VISInst<0b001110000, "fand">;
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def FANDS : VISInst<0b001110001, "fands", FPRegs>;
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def FNAND : VISInst<0b001101110, "fnand">;
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def FNANDS : VISInst<0b001101111, "fnands", FPRegs>;
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def FXOR : VISInst<0b001101100, "fxor">;
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def FXORS : VISInst<0b001101101, "fxors", FPRegs>;
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def FXNOR : VISInst<0b001110010, "fxnor">;
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def FXNORS : VISInst<0b001110011, "fxnors", FPRegs>;
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def FORNOT1 : VISInst<0b001111010, "fornot1">;
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def FORNOT1S : VISInst<0b001111011, "fornot1s", FPRegs>;
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def FORNOT2 : VISInst<0b001110110, "fornot2">;
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def FORNOT2S : VISInst<0b001110111, "fornot2s", FPRegs>;
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def FANDNOT1 : VISInst<0b001101000, "fandnot1">;
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def FANDNOT1S : VISInst<0b001101001, "fandnot1s", FPRegs>;
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def FANDNOT2 : VISInst<0b001100100, "fandnot2">;
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def FANDNOT2S : VISInst<0b001100101, "fandnot2s", FPRegs>;
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def FCMPGT16 : VISInstID<0b000101000, "fcmpgt16">;
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def FCMPGT32 : VISInstID<0b000101100, "fcmpgt32">;
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def FCMPLE16 : VISInstID<0b000100000, "fcmple16">;
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def FCMPLE32 : VISInstID<0b000100100, "fcmple32">;
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def FCMPNE16 : VISInstID<0b000100010, "fcmpne16">;
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def FCMPNE32 : VISInstID<0b000100110, "fcmpne32">;
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def FCMPEQ16 : VISInstID<0b000101010, "fcmpeq16">;
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def FCMPEQ32 : VISInstID<0b000101110, "fcmpeq32">;
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def EDGE8 : VISInst<0b000000000, "edge8", I64Regs>;
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def EDGE8L : VISInst<0b000000010, "edge8l", I64Regs>;
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def EDGE16 : VISInst<0b000000100, "edge16", I64Regs>;
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def EDGE16L : VISInst<0b000000110, "edge16l", I64Regs>;
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def EDGE32 : VISInst<0b000001000, "edge32", I64Regs>;
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def EDGE32L : VISInst<0b000001010, "edge32l", I64Regs>;
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def PDIST : VISInst<0b000111110, "pdist">;
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def ARRAY8 : VISInst<0b000010000, "array8", I64Regs>;
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def ARRAY16 : VISInst<0b000010010, "array16", I64Regs>;
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def ARRAY32 : VISInst<0b000010100, "array32", I64Regs>;
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def SHUTDOWN : VISInst0<0b010000000, "shutdown">;
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} // Predicates = [HasVIS]
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// VIS 2 Instructions.
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let Predicates = [HasVIS2] in {
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def BMASK : VISInst<0b000011001, "bmask", I64Regs>;
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def BSHUFFLE : VISInst<0b001001100, "bshuffle">;
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let rd = 0, rs1 = 0 in
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def SIAM : F3_3_siam<0b10, 0b110110, 0b010000001, (outs),
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(ins i32imm:$mode), "siam $mode", []>;
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def EDGE8N : VISInst<0b000000001, "edge8n", I64Regs>;
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def EDGE8LN : VISInst<0b000000011, "edge8ln", I64Regs>;
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def EDGE16N : VISInst<0b000000101, "edge16n", I64Regs>;
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def EDGE16LN : VISInst<0b000000111, "edge16ln", I64Regs>;
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def EDGE32N : VISInst<0b000001001, "edge32n", I64Regs>;
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def EDGE32LN : VISInst<0b000001011, "edge32ln", I64Regs>;
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} // Predicates = [HasVIS2]
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// VIS 3 Instructions.
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let Predicates = [HasVIS3] in {
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let Uses = [ICC] in
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def ADDXC : VISInst<0b000010001, "addxc", I64Regs>;
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let Defs = [ICC], Uses = [ICC] in
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def ADDXCCC : VISInst<0b000010011, "addxccc", I64Regs>;
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let rd = 0, rs1 = 0 in {
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def CMASK8 : VISInstFormat<0b000011011, (outs), (ins I64Regs:$rs2),
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"cmask8 $rs2">;
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def CMASK16 : VISInstFormat<0b000011101, (outs), (ins I64Regs:$rs2),
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"cmask16 $rs2">;
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def CMASK32 : VISInstFormat<0b000011111, (outs), (ins I64Regs:$rs2),
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"cmask32 $rs2">;
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}
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def FCHKSM16 : VISInst<0b001000100, "fchksm16">;
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def FHADDS : F3_3<0b10, 0b110100, 0b001100001,
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(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fhadds $rs1, $rs2, $rd", []>;
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def FHADDD : F3_3<0b10, 0b110100, 0b001100010,
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(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
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"fhaddd $rs1, $rs2, $rd", []>;
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def FHSUBS : F3_3<0b10, 0b110100, 0b001100101,
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(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fhsubs $rs1, $rs2, $rd", []>;
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def FHSUBD : F3_3<0b10, 0b110100, 0b001100110,
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(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
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"fhsubd $rs1, $rs2, $rd", []>;
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def FLCMPS : VISInstFormat<0b101010001, (outs FCCRegs:$rd),
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(ins FPRegs:$rs1, FPRegs:$rs2),
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"flcmps $rd, $rs1, $rs2">;
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def FLCMPD : VISInstFormat<0b101010010, (outs FCCRegs:$rd),
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(ins DFPRegs:$rs1, DFPRegs:$rs2),
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"flcmpd $rd, $rs1, $rs2">;
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def FMEAN16 : VISInst<0b001000000, "fmean16">;
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def FNADDS : F3_3<0b10, 0b110100, 0b001010001,
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(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fnadds $rs1, $rs2, $rd", []>;
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def FNADDD : F3_3<0b10, 0b110100, 0b001010010,
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(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
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"fnaddd $rs1, $rs2, $rd", []>;
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def FNHADDS : F3_3<0b10, 0b110100, 0b001110001,
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(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fnhadds $rs1, $rs2, $rd", []>;
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def FNHADDD : F3_3<0b10, 0b110100, 0b001110010,
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(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
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"fnhaddd $rs1, $rs2, $rd", []>;
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def FNMULS : F3_3<0b10, 0b110100, 0b001011001,
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(outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fnmuls $rs1, $rs2, $rd", []>;
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def FNMULD : F3_3<0b10, 0b110100, 0b001011010,
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(outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
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"fnmuld $rs1, $rs2, $rd", []>;
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def FNSMULD : F3_3<0b10, 0b110100, 0b001111001,
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(outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
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"fnsmuld $rs1, $rs2, $rd", []>;
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def FPADD64 : VISInst<0b001000010, "fpadd64">;
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def FSLL16 : VISInst<0b000100001, "fsll16">;
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def FSRL16 : VISInst<0b000100011, "fsrl16">;
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def FSLL32 : VISInst<0b000100101, "fsll32">;
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def FSRL32 : VISInst<0b000100111, "fsrl32">;
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def FSLAS16 : VISInst<0b000101001, "fslas16">;
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def FSRA16 : VISInst<0b000101011, "fsra16">;
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def FSLAS32 : VISInst<0b000101101, "fslas32">;
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def FSRA32 : VISInst<0b000101111, "fsra32">;
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let rs1 = 0 in
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def LZCNT : VISInstFormat<0b000010111, (outs I64Regs:$rd),
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(ins I64Regs:$rs2), "lzcnt $rs2, $rd">;
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let rs1 = 0 in {
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def MOVSTOSW : VISInstFormat<0b100010011, (outs IntRegs:$rd),
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(ins FPRegs:$rs2), "movstosw $rs2, $rd">;
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def MOVSTOUW : VISInstFormat<0b100010001, (outs IntRegs:$rd),
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(ins FPRegs:$rs2), "movstouw $rs2, $rd">;
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def MOVDTOX : VISInstFormat<0b100010000, (outs I64Regs:$rd),
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(ins DFPRegs:$rs2), "movdtox $rs2, $rd">;
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def MOVWTOS : VISInstFormat<0b100011001, (outs FPRegs:$rd),
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(ins IntRegs:$rs2), "movwtos $rs2, $rd">;
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def MOVXTOD : VISInstFormat<0b100011000, (outs DFPRegs:$rd),
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(ins I64Regs:$rs2), "movxtod $rs2, $rd">;
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}
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def PDISTN : VISInstID<0b000111111, "pdistn">;
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def UMULXHI : VISInst<0b000010110, "umulxhi", I64Regs>;
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def XMULX : VISInst<0b100010101, "xmulx", I64Regs>;
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def XMULXHI : VISInst<0b100010110, "xmulxhi", I64Regs>;
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} // Predicates = [IsVIS3]
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// FP immediate patterns.
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def fpimm0 : FPImmLeaf<fAny, [{return Imm.isExactlyValue(+0.0);}]>;
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def fpnegimm0 : FPImmLeaf<fAny, [{return Imm.isExactlyValue(-0.0);}]>;
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def fpimmhalf : FPImmLeaf<fAny, [{return Imm.isExactlyValue(+0.5);}]>;
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def fpnegimmhalf : FPImmLeaf<fAny, [{return Imm.isExactlyValue(-0.5);}]>;
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// VIS instruction patterns.
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let Predicates = [HasVIS] in {
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// Zero immediate.
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def : Pat<(f64 fpimm0), (FZERO)>;
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def : Pat<(f32 fpimm0), (FZEROS)>;
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def : Pat<(f64 fpnegimm0), (FNEGD (FZERO))>;
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def : Pat<(f32 fpnegimm0), (FNEGS (FZEROS))>;
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} // Predicates = [HasVIS]
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// VIS3 instruction patterns.
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let Predicates = [HasVIS3] in {
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// +/-0.5 immediate.
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// This is needed to enable halving instructions.
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// FIXME generalize this to arbitrary immediates.
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// SET/MOVWTOS or SETX/MOVXTOD pair should let us materialize FP constants
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// faster than constant pool loading.
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def : Pat<(f32 fpimmhalf), (MOVWTOS (SETHIi 0x0FC000))>;
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def : Pat<(f32 fpnegimmhalf), (MOVWTOS (SETHIi 0x2FC000))>;
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def : Pat<(f64 fpimmhalf), (MOVXTOD (SLLXri (SETHIi 0x0FF800), 32))>;
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def : Pat<(f64 fpnegimmhalf), (MOVXTOD (SLLXri (SETHIi 0x2FF800), 32))>;
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def : Pat<(i64 (adde i64:$lhs, i64:$rhs)), (ADDXCCC $lhs, $rhs)>;
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def : Pat<(i64 (mulhu i64:$lhs, i64:$rhs)), (UMULXHI $lhs, $rhs)>;
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// Signed "MULXHI".
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// Based on the formula presented in OSA2011 §7.140, but with bitops to select
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// the values to be added.
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// TODO: This expansion should probably be moved to DAG legalization phase.
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def : Pat<(i64 (mulhs i64:$lhs, i64:$rhs)),
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(SUBrr (UMULXHI $lhs, $rhs),
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(ADDrr (ANDrr (SRAXri $lhs, 63), $rhs),
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(ANDrr (SRAXri $rhs, 63), $lhs)))>;
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def : Pat<(i64 (ctlz i64:$src)), (LZCNT $src)>;
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def : Pat<(i64 (ctlz_zero_undef i64:$src)), (LZCNT $src)>;
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// 32-bit LZCNT.
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// The zero extension will leave us with 32 extra leading zeros,
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// so we need to compensate for it.
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// FIXME remove this when the codegen supports using 64-bit values directly
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// in V8+ mode.
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def : Pat<(i32 (ctlz i32:$src)), (ADDri (LZCNT (SRLri $src, 0)), (i32 -32))>;
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def : Pat<(i32 (ctlz_zero_undef i32:$src)), (ADDri (LZCNT (SRLri $src, 0)), (i32 -32))>;
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def : Pat<(i32 (bitconvert f32:$src)), (MOVSTOUW $src)>;
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def : Pat<(i64 (zanyext (i32 (bitconvert f32:$src)))), (MOVSTOUW $src)>;
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def : Pat<(i64 (sext (i32 (bitconvert f32:$src)))), (MOVSTOSW $src)>;
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def : Pat<(f32 (bitconvert i32:$src)), (MOVWTOS $src)>;
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def : Pat<(i64 (bitconvert f64:$src)), (MOVDTOX $src)>;
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def : Pat<(f64 (bitconvert i64:$src)), (MOVXTOD $src)>;
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// OP-then-neg FP operations.
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// TODO handle equivalent patterns like `rs1*-rs2`.
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def : Pat<(f32 (fneg (fadd f32:$rs1, f32:$rs2))), (FNADDS $rs1, $rs2)>;
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def : Pat<(f64 (fneg (fadd f64:$rs1, f64:$rs2))), (FNADDD $rs1, $rs2)>;
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def : Pat<(f32 (fneg (fmul f32:$rs1, f32:$rs2))), (FNMULS $rs1, $rs2)>;
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def : Pat<(f64 (fneg (fmul f64:$rs1, f64:$rs2))), (FNMULD $rs1, $rs2)>;
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def : Pat<(f64 (fneg (fmul (fpextend f32:$rs1), (fpextend f32:$rs2)))), (FNSMULD $rs1, $rs2)>;
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// Op-then-halve FP operations.
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def : Pat<(f32 (fmul (fadd f32:$rs1, f32:$rs2), fpimmhalf)), (FHADDS $rs1, $rs2)>;
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def : Pat<(f64 (fmul (fadd f64:$rs1, f64:$rs2), fpimmhalf)), (FHADDD $rs1, $rs2)>;
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def : Pat<(f32 (fmul (fsub f32:$rs1, f32:$rs2), fpimmhalf)), (FHSUBS $rs1, $rs2)>;
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def : Pat<(f64 (fmul (fsub f64:$rs1, f64:$rs2), fpimmhalf)), (FHSUBD $rs1, $rs2)>;
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def : Pat<(f32 (fmul (fadd f32:$rs1, f32:$rs2), fpnegimmhalf)), (FNHADDS $rs1, $rs2)>;
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def : Pat<(f64 (fmul (fadd f64:$rs1, f64:$rs2), fpnegimmhalf)), (FNHADDD $rs1, $rs2)>;
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} // Predicates = [HasVIS3]
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