63de20c0de
This fixes #139614 on non-clang compilers by moving `__has_warning` completely inside the `#if defined(__clang__)` block. This prevents a parse failure from compilers which don't recognize `__has_warning`. Original description: Followup to #138741. This adds the requested macro to silence `-Wunnecessary-virtual-specifier` when declaring virtual anchor functions in `final` classes, per [LLVM policy](https://llvm.org/docs/CodingStandards.html#provide-a-virtual-method-anchor-for-classes-in-headers). It also cleans up any remaining instances of the warning, allowing us to stop disabling it when we build LLVM.
777 lines
34 KiB
C++
777 lines
34 KiB
C++
//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the X86 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
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#define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "X86InstrFMA3Info.h"
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#include "X86RegisterInfo.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include <vector>
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#define GET_INSTRINFO_HEADER
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#include "X86GenInstrInfo.inc"
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namespace llvm {
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class X86Subtarget;
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// X86 MachineCombiner patterns
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enum X86MachineCombinerPattern : unsigned {
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// X86 VNNI
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DPWSSD = MachineCombinerPattern::TARGET_PATTERN_START,
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};
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namespace X86 {
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enum AsmComments {
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// For instr that was compressed from EVEX to LEGACY.
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AC_EVEX_2_LEGACY = MachineInstr::TAsmComments,
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// For instr that was compressed from EVEX to VEX.
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AC_EVEX_2_VEX = AC_EVEX_2_LEGACY << 1,
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// For instr that was compressed from EVEX to EVEX.
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AC_EVEX_2_EVEX = AC_EVEX_2_VEX << 1
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};
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/// Return a pair of condition code for the given predicate and whether
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/// the instruction operands should be swaped to match the condition code.
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std::pair<CondCode, bool> getX86ConditionCode(CmpInst::Predicate Predicate);
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/// Return a cmov opcode for the given register size in bytes, and operand type.
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unsigned getCMovOpcode(unsigned RegBytes, bool HasMemoryOperand = false,
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bool HasNDD = false);
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/// Return the source operand # for condition code by \p MCID. If the
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/// instruction doesn't have a condition code, return -1.
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int getCondSrcNoFromDesc(const MCInstrDesc &MCID);
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/// Return the condition code of the instruction. If the instruction doesn't
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/// have a condition code, return X86::COND_INVALID.
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CondCode getCondFromMI(const MachineInstr &MI);
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// Turn JCC instruction into condition code.
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CondCode getCondFromBranch(const MachineInstr &MI);
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// Turn SETCC instruction into condition code.
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CondCode getCondFromSETCC(const MachineInstr &MI);
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// Turn CMOV instruction into condition code.
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CondCode getCondFromCMov(const MachineInstr &MI);
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// Turn CFCMOV instruction into condition code.
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CondCode getCondFromCFCMov(const MachineInstr &MI);
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// Turn CCMP instruction into condition code.
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CondCode getCondFromCCMP(const MachineInstr &MI);
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// Turn condition code into condition flags for CCMP/CTEST.
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int getCCMPCondFlagsFromCondCode(CondCode CC);
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// Get the opcode of corresponding NF variant.
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unsigned getNFVariant(unsigned Opc);
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// Get the opcode of corresponding NonND variant.
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unsigned getNonNDVariant(unsigned Opc);
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/// GetOppositeBranchCondition - Return the inverse of the specified cond,
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/// e.g. turning COND_E to COND_NE.
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CondCode GetOppositeBranchCondition(CondCode CC);
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/// Get the VPCMP immediate for the given condition.
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unsigned getVPCMPImmForCond(ISD::CondCode CC);
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/// Get the VPCMP immediate if the opcodes are swapped.
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unsigned getSwappedVPCMPImm(unsigned Imm);
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/// Get the VPCOM immediate if the opcodes are swapped.
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unsigned getSwappedVPCOMImm(unsigned Imm);
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/// Get the VCMP immediate if the opcodes are swapped.
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unsigned getSwappedVCMPImm(unsigned Imm);
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/// Get the width of the vector register operand.
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unsigned getVectorRegisterWidth(const MCOperandInfo &Info);
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/// Check if the instruction is X87 instruction.
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bool isX87Instruction(MachineInstr &MI);
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/// Return the index of the instruction's first address operand, if it has a
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/// memory reference, or -1 if it has none. Unlike X86II::getMemoryOperandNo(),
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/// this also works for both pseudo instructions (e.g., TCRETURNmi) as well as
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/// real instructions (e.g., JMP64m).
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int getFirstAddrOperandIdx(const MachineInstr &MI);
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/// Find any constant pool entry associated with a specific instruction operand.
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const Constant *getConstantFromPool(const MachineInstr &MI, unsigned OpNo);
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} // namespace X86
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/// isGlobalStubReference - Return true if the specified TargetFlag operand is
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/// a reference to a stub for a global, not the global itself.
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inline static bool isGlobalStubReference(unsigned char TargetFlag) {
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switch (TargetFlag) {
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case X86II::MO_DLLIMPORT: // dllimport stub.
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case X86II::MO_GOTPCREL: // rip-relative GOT reference.
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case X86II::MO_GOTPCREL_NORELAX: // rip-relative GOT reference.
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case X86II::MO_GOT: // normal GOT reference.
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
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case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
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case X86II::MO_COFFSTUB: // COFF .refptr stub.
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return true;
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default:
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return false;
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}
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}
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/// isGlobalRelativeToPICBase - Return true if the specified global value
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/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
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/// is true, the addressing mode has the PIC base register added in (e.g. EBX).
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inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
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switch (TargetFlag) {
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case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
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case X86II::MO_GOT: // isPICStyleGOT: other global.
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case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
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case X86II::MO_TLVP: // ??? Pretty sure..
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return true;
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default:
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return false;
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}
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}
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inline static bool isScale(const MachineOperand &MO) {
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return MO.isImm() && (MO.getImm() == 1 || MO.getImm() == 2 ||
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MO.getImm() == 4 || MO.getImm() == 8);
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}
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inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) {
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if (MI.getOperand(Op).isFI())
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return true;
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return Op + X86::AddrSegmentReg <= MI.getNumOperands() &&
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MI.getOperand(Op + X86::AddrBaseReg).isReg() &&
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isScale(MI.getOperand(Op + X86::AddrScaleAmt)) &&
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MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
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(MI.getOperand(Op + X86::AddrDisp).isImm() ||
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MI.getOperand(Op + X86::AddrDisp).isGlobal() ||
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MI.getOperand(Op + X86::AddrDisp).isCPI() ||
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MI.getOperand(Op + X86::AddrDisp).isJTI());
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}
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inline static bool isMem(const MachineInstr &MI, unsigned Op) {
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if (MI.getOperand(Op).isFI())
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return true;
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return Op + X86::AddrNumOperands <= MI.getNumOperands() &&
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MI.getOperand(Op + X86::AddrSegmentReg).isReg() && isLeaMem(MI, Op);
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}
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inline static bool isAddMemInstrWithRelocation(const MachineInstr &MI) {
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unsigned Op = MI.getOpcode();
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if (Op == X86::ADD64rm || Op == X86::ADD64mr_ND || Op == X86::ADD64rm_ND) {
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int MemOpNo = X86II::getMemoryOperandNo(MI.getDesc().TSFlags) +
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X86II::getOperandBias(MI.getDesc());
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const MachineOperand &MO = MI.getOperand(X86::AddrDisp + MemOpNo);
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if (MO.getTargetFlags() == X86II::MO_GOTTPOFF)
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return true;
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}
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return false;
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}
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inline static bool isMemInstrWithGOTPCREL(const MachineInstr &MI) {
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unsigned Op = MI.getOpcode();
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switch (Op) {
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case X86::TEST32mr:
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case X86::TEST64mr:
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case X86::CMP32rm:
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case X86::CMP64rm:
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case X86::MOV32rm:
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case X86::MOV64rm:
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case X86::ADC32rm:
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case X86::ADD32rm:
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case X86::AND32rm:
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case X86::OR32rm:
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case X86::SBB32rm:
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case X86::SUB32rm:
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case X86::XOR32rm:
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case X86::ADC64rm:
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case X86::ADD64rm:
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case X86::AND64rm:
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case X86::OR64rm:
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case X86::SBB64rm:
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case X86::SUB64rm:
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case X86::XOR64rm: {
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int MemOpNo = X86II::getMemoryOperandNo(MI.getDesc().TSFlags) +
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X86II::getOperandBias(MI.getDesc());
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const MachineOperand &MO = MI.getOperand(X86::AddrDisp + MemOpNo);
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if (MO.getTargetFlags() == X86II::MO_GOTPCREL)
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return true;
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break;
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}
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}
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return false;
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}
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class X86InstrInfo final : public X86GenInstrInfo {
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X86Subtarget &Subtarget;
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const X86RegisterInfo RI;
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LLVM_DECLARE_VIRTUAL_ANCHOR_FUNCTION();
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bool analyzeBranchImpl(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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SmallVectorImpl<MachineInstr *> &CondBranches,
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bool AllowModify) const;
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bool foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, Register Reg,
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int64_t ImmVal, MachineRegisterInfo *MRI,
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bool MakeChange) const;
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public:
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explicit X86InstrInfo(X86Subtarget &STI);
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/// Given a machine instruction descriptor, returns the register
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/// class constraint for OpNum, or NULL. Returned register class
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/// may be different from the definition in the TD file, e.g.
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/// GR*RegClass (definition in TD file)
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/// ->
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/// GR*_NOREX2RegClass (Returned register class)
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const TargetRegisterClass *
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getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
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const TargetRegisterInfo *TRI,
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const MachineFunction &MF) const override;
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const X86RegisterInfo &getRegisterInfo() const { return RI; }
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/// Returns the stack pointer adjustment that happens inside the frame
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/// setup..destroy sequence (e.g. by pushes, or inside the callee).
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int64_t getFrameAdjustment(const MachineInstr &I) const {
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assert(isFrameInstr(I));
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if (isFrameSetup(I))
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return I.getOperand(2).getImm();
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return I.getOperand(1).getImm();
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}
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/// Sets the stack pointer adjustment made inside the frame made up by this
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/// instruction.
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void setFrameAdjustment(MachineInstr &I, int64_t V) const {
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assert(isFrameInstr(I));
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if (isFrameSetup(I))
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I.getOperand(2).setImm(V);
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else
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I.getOperand(1).setImm(V);
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}
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/// getSPAdjust - This returns the stack pointer adjustment made by
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/// this instruction. For x86, we need to handle more complex call
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/// sequences involving PUSHes.
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int getSPAdjust(const MachineInstr &MI) const override;
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/// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
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/// extension instruction. That is, it's like a copy where it's legal for the
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/// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
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/// true, then it's expected the pre-extension value is available as a subreg
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/// of the result register. This also returns the sub-register index in
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/// SubIdx.
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bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
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Register &DstReg, unsigned &SubIdx) const override;
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/// Returns true if the instruction has no behavior (specified or otherwise)
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/// that is based on the value of any of its register operands
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///
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/// Instructions are considered data invariant even if they set EFLAGS.
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///
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/// A classical example of something that is inherently not data invariant is
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/// an indirect jump -- the destination is loaded into icache based on the
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/// bits set in the jump destination register.
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///
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/// FIXME: This should become part of our instruction tables.
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static bool isDataInvariant(MachineInstr &MI);
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/// Returns true if the instruction has no behavior (specified or otherwise)
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/// that is based on the value loaded from memory or the value of any
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/// non-address register operands.
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///
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/// For example, if the latency of the instruction is dependent on the
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/// particular bits set in any of the registers *or* any of the bits loaded
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/// from memory.
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///
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/// Instructions are considered data invariant even if they set EFLAGS.
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///
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/// A classical example of something that is inherently not data invariant is
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/// an indirect jump -- the destination is loaded into icache based on the
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/// bits set in the jump destination register.
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///
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/// FIXME: This should become part of our instruction tables.
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static bool isDataInvariantLoad(MachineInstr &MI);
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Register isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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Register isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex,
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TypeSize &MemBytes) const override;
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/// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
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/// stack locations as well. This uses a heuristic so it isn't
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/// reliable for correctness.
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Register isLoadFromStackSlotPostFE(const MachineInstr &MI,
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int &FrameIndex) const override;
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Register isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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Register isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex,
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TypeSize &MemBytes) const override;
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/// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
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/// stack locations as well. This uses a heuristic so it isn't
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/// reliable for correctness.
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Register isStoreToStackSlotPostFE(const MachineInstr &MI,
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int &FrameIndex) const override;
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bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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Register DestReg, unsigned SubIdx,
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const MachineInstr &Orig,
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const TargetRegisterInfo &TRI) const override;
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/// Given an operand within a MachineInstr, insert preceding code to put it
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/// into the right format for a particular kind of LEA instruction. This may
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/// involve using an appropriate super-register instead (with an implicit use
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/// of the original) or creating a new virtual register and inserting COPY
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/// instructions to get the data into the right class.
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///
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/// Reference parameters are set to indicate how caller should add this
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/// operand to the LEA instruction.
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bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
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unsigned LEAOpcode, bool AllowSP, Register &NewSrc,
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unsigned &NewSrcSubReg, bool &isKill,
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MachineOperand &ImplicitOp, LiveVariables *LV,
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LiveIntervals *LIS) const;
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into a true
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/// three-address instruction on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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///
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the new instruction.
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///
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MachineInstr *convertToThreeAddress(MachineInstr &MI, LiveVariables *LV,
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LiveIntervals *LIS) const override;
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/// Returns true iff the routine could find two commutable operands in the
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/// given machine instruction.
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/// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
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/// input values can be re-defined in this method only if the input values
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/// are not pre-defined, which is designated by the special value
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/// 'CommuteAnyOperandIndex' assigned to it.
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/// If both of indices are pre-defined and refer to some operands, then the
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/// method simply returns true if the corresponding operands are commutable
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/// and returns false otherwise.
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///
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/// For example, calling this method this way:
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/// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
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/// findCommutedOpIndices(MI, Op1, Op2);
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/// can be interpreted as a query asking to find an operand that would be
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/// commutable with the operand#1.
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bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
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unsigned &SrcOpIdx2) const override;
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/// Returns true if we have preference on the operands order in MI, the
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/// commute decision is returned in Commute.
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bool hasCommutePreference(MachineInstr &MI, bool &Commute) const override;
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/// Returns an adjusted FMA opcode that must be used in FMA instruction that
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/// performs the same computations as the given \p MI but which has the
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/// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
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/// It may return 0 if it is unsafe to commute the operands.
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/// Note that a machine instruction (instead of its opcode) is passed as the
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/// first parameter to make it possible to analyze the instruction's uses and
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/// commute the first operand of FMA even when it seems unsafe when you look
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/// at the opcode. For example, it is Ok to commute the first operand of
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/// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
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///
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/// The returned FMA opcode may differ from the opcode in the given \p MI.
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/// For example, commuting the operands #1 and #3 in the following FMA
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/// FMA213 #1, #2, #3
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/// results into instruction with adjusted opcode:
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/// FMA231 #3, #2, #1
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unsigned
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getFMA3OpcodeToCommuteOperands(const MachineInstr &MI, unsigned SrcOpIdx1,
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unsigned SrcOpIdx2,
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const X86InstrFMA3Group &FMA3Group) const;
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// Branch analysis.
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bool isUnconditionalTailCall(const MachineInstr &MI) const override;
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bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond,
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const MachineInstr &TailCall) const override;
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void replaceBranchWithTailCall(MachineBasicBlock &MBB,
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SmallVectorImpl<MachineOperand> &Cond,
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const MachineInstr &TailCall) const override;
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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int getJumpTableIndex(const MachineInstr &MI) const override;
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std::optional<ExtAddrMode>
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getAddrModeFromMemoryOp(const MachineInstr &MemI,
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const TargetRegisterInfo *TRI) const override;
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bool getConstValDefinedInReg(const MachineInstr &MI, const Register Reg,
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int64_t &ImmVal) const override;
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bool preservesZeroValueInReg(const MachineInstr *MI,
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const Register NullValueReg,
|
|
const TargetRegisterInfo *TRI) const override;
|
|
|
|
bool getMemOperandsWithOffsetWidth(
|
|
const MachineInstr &LdSt,
|
|
SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
|
|
bool &OffsetIsScalable, LocationSize &Width,
|
|
const TargetRegisterInfo *TRI) const override;
|
|
bool analyzeBranchPredicate(MachineBasicBlock &MBB,
|
|
TargetInstrInfo::MachineBranchPredicate &MBP,
|
|
bool AllowModify = false) const override;
|
|
|
|
unsigned removeBranch(MachineBasicBlock &MBB,
|
|
int *BytesRemoved = nullptr) const override;
|
|
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
|
|
const DebugLoc &DL,
|
|
int *BytesAdded = nullptr) const override;
|
|
bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
|
|
Register, Register, Register, int &, int &,
|
|
int &) const override;
|
|
void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
const DebugLoc &DL, Register DstReg,
|
|
ArrayRef<MachineOperand> Cond, Register TrueReg,
|
|
Register FalseReg) const override;
|
|
void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
const DebugLoc &DL, Register DestReg, Register SrcReg,
|
|
bool KillSrc, bool RenamableDest = false,
|
|
bool RenamableSrc = false) const override;
|
|
void storeRegToStackSlot(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register SrcReg,
|
|
bool isKill, int FrameIndex, const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI, Register VReg,
|
|
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
|
|
|
|
void loadRegFromStackSlot(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg,
|
|
int FrameIndex, const TargetRegisterClass *RC,
|
|
const TargetRegisterInfo *TRI, Register VReg,
|
|
MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
|
|
|
|
void loadStoreTileReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
|
unsigned Opc, Register Reg, int FrameIdx,
|
|
bool isKill = false) const;
|
|
|
|
bool expandPostRAPseudo(MachineInstr &MI) const override;
|
|
|
|
/// Check whether the target can fold a load that feeds a subreg operand
|
|
/// (or a subreg operand that feeds a store).
|
|
bool isSubregFoldable() const override { return true; }
|
|
|
|
/// Fold a load or store of the specified stack slot into the specified
|
|
/// machine instruction for the specified operand(s). If folding happens, it
|
|
/// is likely that the referenced instruction has been changed.
|
|
///
|
|
/// \returns true on success.
|
|
MachineInstr *
|
|
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
|
|
ArrayRef<unsigned> Ops,
|
|
MachineBasicBlock::iterator InsertPt, int FrameIndex,
|
|
LiveIntervals *LIS = nullptr,
|
|
VirtRegMap *VRM = nullptr) const override;
|
|
|
|
/// Same as the previous version except it allows folding of any load and
|
|
/// store from / to any address, not just from a specific stack slot.
|
|
MachineInstr *foldMemoryOperandImpl(
|
|
MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
|
|
MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
|
|
LiveIntervals *LIS = nullptr) const override;
|
|
|
|
bool
|
|
unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, Register Reg,
|
|
bool UnfoldLoad, bool UnfoldStore,
|
|
SmallVectorImpl<MachineInstr *> &NewMIs) const override;
|
|
|
|
bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
|
|
SmallVectorImpl<SDNode *> &NewNodes) const override;
|
|
|
|
unsigned
|
|
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore,
|
|
unsigned *LoadRegIndex = nullptr) const override;
|
|
|
|
bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
|
|
int64_t &Offset2) const override;
|
|
|
|
/// Overrides the isSchedulingBoundary from Codegen/TargetInstrInfo.cpp to
|
|
/// make it capable of identifying ENDBR intructions and prevent it from being
|
|
/// re-scheduled.
|
|
bool isSchedulingBoundary(const MachineInstr &MI,
|
|
const MachineBasicBlock *MBB,
|
|
const MachineFunction &MF) const override;
|
|
|
|
/// This is a used by the pre-regalloc scheduler to determine (in conjunction
|
|
/// with areLoadsFromSameBasePtr) if two loads should be scheduled togther. On
|
|
/// some targets if two loads are loading from addresses in the same cache
|
|
/// line, it's better if they are scheduled together. This function takes two
|
|
/// integers that represent the load offsets from the common base address. It
|
|
/// returns true if it decides it's desirable to schedule the two loads
|
|
/// together. "NumLoads" is the number of loads that have already been
|
|
/// scheduled after Load1.
|
|
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1,
|
|
int64_t Offset2,
|
|
unsigned NumLoads) const override;
|
|
|
|
void insertNoop(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator MI) const override;
|
|
|
|
MCInst getNop() const override;
|
|
|
|
bool
|
|
reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
|
|
|
|
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
|
|
|
|
/// True if MI has a condition code def, e.g. EFLAGS, that is
|
|
/// not marked dead.
|
|
bool hasLiveCondCodeDef(MachineInstr &MI) const;
|
|
|
|
/// getGlobalBaseReg - Return a virtual register initialized with the
|
|
/// the global base register value. Output instructions required to
|
|
/// initialize the register in the function entry block, if necessary.
|
|
///
|
|
Register getGlobalBaseReg(MachineFunction *MF) const;
|
|
|
|
std::pair<uint16_t, uint16_t>
|
|
getExecutionDomain(const MachineInstr &MI) const override;
|
|
|
|
uint16_t getExecutionDomainCustom(const MachineInstr &MI) const;
|
|
|
|
void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
|
|
|
|
bool setExecutionDomainCustom(MachineInstr &MI, unsigned Domain) const;
|
|
|
|
unsigned
|
|
getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum,
|
|
const TargetRegisterInfo *TRI) const override;
|
|
unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum,
|
|
const TargetRegisterInfo *TRI) const override;
|
|
void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum,
|
|
const TargetRegisterInfo *TRI) const override;
|
|
|
|
MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
|
|
unsigned OpNum,
|
|
ArrayRef<MachineOperand> MOs,
|
|
MachineBasicBlock::iterator InsertPt,
|
|
unsigned Size, Align Alignment,
|
|
bool AllowCommute) const;
|
|
|
|
bool isHighLatencyDef(int opc) const override;
|
|
|
|
bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
|
|
const MachineRegisterInfo *MRI,
|
|
const MachineInstr &DefMI, unsigned DefIdx,
|
|
const MachineInstr &UseMI,
|
|
unsigned UseIdx) const override;
|
|
|
|
bool useMachineCombiner() const override { return true; }
|
|
|
|
bool isAssociativeAndCommutative(const MachineInstr &Inst,
|
|
bool Invert) const override;
|
|
|
|
bool hasReassociableOperands(const MachineInstr &Inst,
|
|
const MachineBasicBlock *MBB) const override;
|
|
|
|
void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
|
|
MachineInstr &NewMI1,
|
|
MachineInstr &NewMI2) const override;
|
|
|
|
bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
|
|
Register &SrcReg2, int64_t &CmpMask,
|
|
int64_t &CmpValue) const override;
|
|
|
|
/// Check if there exists an earlier instruction that operates on the same
|
|
/// source operands and sets eflags in the same way as CMP and remove CMP if
|
|
/// possible.
|
|
bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
|
|
Register SrcReg2, int64_t CmpMask, int64_t CmpValue,
|
|
const MachineRegisterInfo *MRI) const override;
|
|
|
|
bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
|
|
MachineRegisterInfo *MRI) const override;
|
|
|
|
std::pair<unsigned, unsigned>
|
|
decomposeMachineOperandsTargetFlags(unsigned TF) const override;
|
|
|
|
ArrayRef<std::pair<unsigned, const char *>>
|
|
getSerializableDirectMachineOperandTargetFlags() const override;
|
|
|
|
std::optional<std::unique_ptr<outliner::OutlinedFunction>>
|
|
getOutliningCandidateInfo(
|
|
const MachineModuleInfo &MMI,
|
|
std::vector<outliner::Candidate> &RepeatedSequenceLocs,
|
|
unsigned MinRepeats) const override;
|
|
|
|
bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
|
|
bool OutlineFromLinkOnceODRs) const override;
|
|
|
|
outliner::InstrType getOutliningTypeImpl(const MachineModuleInfo &MMI,
|
|
MachineBasicBlock::iterator &MIT,
|
|
unsigned Flags) const override;
|
|
|
|
void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
|
|
const outliner::OutlinedFunction &OF) const override;
|
|
|
|
MachineBasicBlock::iterator
|
|
insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator &It, MachineFunction &MF,
|
|
outliner::Candidate &C) const override;
|
|
|
|
void buildClearRegister(Register Reg, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator Iter, DebugLoc &DL,
|
|
bool AllowSideEffects = true) const override;
|
|
|
|
bool verifyInstruction(const MachineInstr &MI,
|
|
StringRef &ErrInfo) const override;
|
|
#define GET_INSTRINFO_HELPER_DECLS
|
|
#include "X86GenInstrInfo.inc"
|
|
|
|
static bool hasLockPrefix(const MachineInstr &MI) {
|
|
return MI.getDesc().TSFlags & X86II::LOCK;
|
|
}
|
|
|
|
std::optional<ParamLoadedValue>
|
|
describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
|
|
|
|
protected:
|
|
MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
|
|
unsigned CommuteOpIdx1,
|
|
unsigned CommuteOpIdx2) const override;
|
|
|
|
std::optional<DestSourcePair>
|
|
isCopyInstrImpl(const MachineInstr &MI) const override;
|
|
|
|
bool getMachineCombinerPatterns(MachineInstr &Root,
|
|
SmallVectorImpl<unsigned> &Patterns,
|
|
bool DoRegPressureReduce) const override;
|
|
|
|
/// When getMachineCombinerPatterns() finds potential patterns,
|
|
/// this function generates the instructions that could replace the
|
|
/// original code sequence.
|
|
void genAlternativeCodeSequence(
|
|
MachineInstr &Root, unsigned Pattern,
|
|
SmallVectorImpl<MachineInstr *> &InsInstrs,
|
|
SmallVectorImpl<MachineInstr *> &DelInstrs,
|
|
DenseMap<Register, unsigned> &InstrIdxForVirtReg) const override;
|
|
|
|
/// When calculate the latency of the root instruction, accumulate the
|
|
/// latency of the sequence to the root latency.
|
|
/// \param Root - Instruction that could be combined with one of its operands
|
|
/// For X86 instruction (vpmaddwd + vpmaddwd) -> vpdpwssd, the vpmaddwd
|
|
/// is not in the critical path, so the root latency only include vpmaddwd.
|
|
bool accumulateInstrSeqToRootLatency(MachineInstr &Root) const override {
|
|
return false;
|
|
}
|
|
|
|
void getFrameIndexOperands(SmallVectorImpl<MachineOperand> &Ops,
|
|
int FI) const override;
|
|
|
|
private:
|
|
/// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
|
|
/// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
|
|
/// super-register and then truncating back down to a 8/16-bit sub-register.
|
|
MachineInstr *convertToThreeAddressWithLEA(unsigned MIOpc, MachineInstr &MI,
|
|
LiveVariables *LV,
|
|
LiveIntervals *LIS,
|
|
bool Is8BitOp) const;
|
|
|
|
/// Handles memory folding for special case instructions, for instance those
|
|
/// requiring custom manipulation of the address.
|
|
MachineInstr *foldMemoryOperandCustom(MachineFunction &MF, MachineInstr &MI,
|
|
unsigned OpNum,
|
|
ArrayRef<MachineOperand> MOs,
|
|
MachineBasicBlock::iterator InsertPt,
|
|
unsigned Size, Align Alignment) const;
|
|
|
|
MachineInstr *foldMemoryBroadcast(MachineFunction &MF, MachineInstr &MI,
|
|
unsigned OpNum,
|
|
ArrayRef<MachineOperand> MOs,
|
|
MachineBasicBlock::iterator InsertPt,
|
|
unsigned BitsSize, bool AllowCommute) const;
|
|
|
|
/// isFrameOperand - Return true and the FrameIndex if the specified
|
|
/// operand and follow operands form a reference to the stack frame.
|
|
bool isFrameOperand(const MachineInstr &MI, unsigned int Op,
|
|
int &FrameIndex) const;
|
|
|
|
/// Returns true iff the routine could find two commutable operands in the
|
|
/// given machine instruction with 3 vector inputs.
|
|
/// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
|
|
/// input values can be re-defined in this method only if the input values
|
|
/// are not pre-defined, which is designated by the special value
|
|
/// 'CommuteAnyOperandIndex' assigned to it.
|
|
/// If both of indices are pre-defined and refer to some operands, then the
|
|
/// method simply returns true if the corresponding operands are commutable
|
|
/// and returns false otherwise.
|
|
///
|
|
/// For example, calling this method this way:
|
|
/// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
|
|
/// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
|
|
/// can be interpreted as a query asking to find an operand that would be
|
|
/// commutable with the operand#1.
|
|
///
|
|
/// If IsIntrinsic is set, operand 1 will be ignored for commuting.
|
|
bool findThreeSrcCommutedOpIndices(const MachineInstr &MI,
|
|
unsigned &SrcOpIdx1,
|
|
unsigned &SrcOpIdx2,
|
|
bool IsIntrinsic = false) const;
|
|
|
|
/// Returns true when instruction \p FlagI produces the same flags as \p OI.
|
|
/// The caller should pass in the results of calling analyzeCompare on \p OI:
|
|
/// \p SrcReg, \p SrcReg2, \p ImmMask, \p ImmValue.
|
|
/// If the flags match \p OI as if it had the input operands swapped then the
|
|
/// function succeeds and sets \p IsSwapped to true.
|
|
///
|
|
/// Examples of OI, FlagI pairs returning true:
|
|
/// CMP %1, 42 and CMP %1, 42
|
|
/// CMP %1, %2 and %3 = SUB %1, %2
|
|
/// TEST %1, %1 and %2 = SUB %1, 0
|
|
/// CMP %1, %2 and %3 = SUB %2, %1 ; IsSwapped=true
|
|
bool isRedundantFlagInstr(const MachineInstr &FlagI, Register SrcReg,
|
|
Register SrcReg2, int64_t ImmMask, int64_t ImmValue,
|
|
const MachineInstr &OI, bool *IsSwapped,
|
|
int64_t *ImmDelta) const;
|
|
|
|
/// Commute operands of \p MI for memory fold.
|
|
///
|
|
/// \param Idx1 the index of operand to be commuted.
|
|
///
|
|
/// \returns the index of operand that is commuted with \p Idx1. If the method
|
|
/// fails to commute the operands, it will return \p Idx1.
|
|
unsigned commuteOperandsForFold(MachineInstr &MI, unsigned Idx1) const;
|
|
};
|
|
} // namespace llvm
|
|
|
|
#endif
|