c91f2a259f
We use 'k' for move instructions and to indicate masked variants of evex instructions, but otherwise we're very inconsistent when we use 'k' vs 'r'.
488 lines
22 KiB
TableGen
488 lines
22 KiB
TableGen
//===- X86InstrVecCompiler.td - Vector Compiler Patterns ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the various vector pseudo instructions used by the
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// compiler, as well as Pat patterns used during instruction selection.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Non-instruction patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [NoAVX512] in {
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// A vector extract of the first f32/f64 position is a subregister copy
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def : Pat<(f16 (extractelt (v8f16 VR128:$src), (iPTR 0))),
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(COPY_TO_REGCLASS (v8f16 VR128:$src), FR16)>;
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def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
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(COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
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def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
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(COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
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}
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let Predicates = [HasAVX512] in {
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// A vector extract of the first f32/f64 position is a subregister copy
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def : Pat<(f16 (extractelt (v8f16 VR128X:$src), (iPTR 0))),
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(COPY_TO_REGCLASS (v8f16 VR128X:$src), FR16X)>;
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def : Pat<(f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))),
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(COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X)>;
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def : Pat<(f64 (extractelt (v2f64 VR128X:$src), (iPTR 0))),
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(COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X)>;
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}
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let Predicates = [NoVLX] in {
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def : Pat<(v8f16 (scalar_to_vector FR16:$src)),
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(COPY_TO_REGCLASS FR16:$src, VR128)>;
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// Implicitly promote a 32-bit scalar to a vector.
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def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
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(COPY_TO_REGCLASS FR32:$src, VR128)>;
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// Implicitly promote a 64-bit scalar to a vector.
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def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
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(COPY_TO_REGCLASS FR64:$src, VR128)>;
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}
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let Predicates = [HasVLX] in {
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def : Pat<(v8f16 (scalar_to_vector FR16X:$src)),
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(COPY_TO_REGCLASS FR16X:$src, VR128X)>;
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// Implicitly promote a 32-bit scalar to a vector.
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def : Pat<(v4f32 (scalar_to_vector FR32X:$src)),
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(COPY_TO_REGCLASS FR32X:$src, VR128X)>;
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// Implicitly promote a 64-bit scalar to a vector.
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def : Pat<(v2f64 (scalar_to_vector FR64X:$src)),
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(COPY_TO_REGCLASS FR64X:$src, VR128X)>;
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}
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//===----------------------------------------------------------------------===//
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// Subvector tricks
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//===----------------------------------------------------------------------===//
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// Patterns for insert_subvector/extract_subvector to/from index=0
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multiclass subvector_subreg_lowering<RegisterClass subRC, ValueType subVT,
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RegisterClass RC, ValueType VT,
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SubRegIndex subIdx> {
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def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))),
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(subVT (EXTRACT_SUBREG RC:$src, subIdx))>;
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def : Pat<(VT (insert_subvector undef_or_freeze_undef, subRC:$src, (iPTR 0))),
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(VT (INSERT_SUBREG (IMPLICIT_DEF), subRC:$src, subIdx))>;
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}
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// A 128-bit subvector extract from the first 256-bit vector position is a
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// subregister copy that needs no instruction. Likewise, a 128-bit subvector
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// insert to the first 256-bit vector position is a subregister copy that needs
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// no instruction.
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defm : subvector_subreg_lowering<VR128, v4i32, VR256, v8i32, sub_xmm>;
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defm : subvector_subreg_lowering<VR128, v4f32, VR256, v8f32, sub_xmm>;
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defm : subvector_subreg_lowering<VR128, v2i64, VR256, v4i64, sub_xmm>;
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defm : subvector_subreg_lowering<VR128, v2f64, VR256, v4f64, sub_xmm>;
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defm : subvector_subreg_lowering<VR128, v8i16, VR256, v16i16, sub_xmm>;
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defm : subvector_subreg_lowering<VR128, v16i8, VR256, v32i8, sub_xmm>;
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defm : subvector_subreg_lowering<VR128, v8f16, VR256, v16f16, sub_xmm>;
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defm : subvector_subreg_lowering<VR128, v8bf16, VR256, v16bf16, sub_xmm>;
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// A 128-bit subvector extract from the first 512-bit vector position is a
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// subregister copy that needs no instruction. Likewise, a 128-bit subvector
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// insert to the first 512-bit vector position is a subregister copy that needs
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// no instruction.
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defm : subvector_subreg_lowering<VR128, v4i32, VR512, v16i32, sub_xmm>;
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defm : subvector_subreg_lowering<VR128, v4f32, VR512, v16f32, sub_xmm>;
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defm : subvector_subreg_lowering<VR128, v2i64, VR512, v8i64, sub_xmm>;
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defm : subvector_subreg_lowering<VR128, v2f64, VR512, v8f64, sub_xmm>;
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defm : subvector_subreg_lowering<VR128, v8i16, VR512, v32i16, sub_xmm>;
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defm : subvector_subreg_lowering<VR128, v16i8, VR512, v64i8, sub_xmm>;
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defm : subvector_subreg_lowering<VR128, v8f16, VR512, v32f16, sub_xmm>;
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defm : subvector_subreg_lowering<VR128, v8bf16, VR512, v32bf16, sub_xmm>;
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// A 128-bit subvector extract from the first 512-bit vector position is a
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// subregister copy that needs no instruction. Likewise, a 128-bit subvector
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// insert to the first 512-bit vector position is a subregister copy that needs
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// no instruction.
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defm : subvector_subreg_lowering<VR256, v8i32, VR512, v16i32, sub_ymm>;
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defm : subvector_subreg_lowering<VR256, v8f32, VR512, v16f32, sub_ymm>;
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defm : subvector_subreg_lowering<VR256, v4i64, VR512, v8i64, sub_ymm>;
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defm : subvector_subreg_lowering<VR256, v4f64, VR512, v8f64, sub_ymm>;
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defm : subvector_subreg_lowering<VR256, v16i16, VR512, v32i16, sub_ymm>;
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defm : subvector_subreg_lowering<VR256, v32i8, VR512, v64i8, sub_ymm>;
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defm : subvector_subreg_lowering<VR256, v16f16, VR512, v32f16, sub_ymm>;
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defm : subvector_subreg_lowering<VR256, v16bf16, VR512, v32bf16, sub_ymm>;
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// If we're inserting into an all zeros vector, just use a plain move which
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// will zero the upper bits. A post-isel hook will take care of removing
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// any moves that we can prove are unnecessary.
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multiclass subvec_zero_lowering<string MoveStr,
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RegisterClass RC, ValueType DstTy,
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ValueType SrcTy, SubRegIndex SubIdx> {
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def : Pat<(DstTy (insert_subvector immAllZerosV,
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(SrcTy RC:$src), (iPTR 0))),
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(SUBREG_TO_REG (i64 0),
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(SrcTy (!cast<Instruction>("VMOV"#MoveStr#"rr") RC:$src)), SubIdx)>;
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}
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let Predicates = [HasAVX, NoVLX] in {
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defm : subvec_zero_lowering<"APD", VR128, v4f64, v2f64, sub_xmm>;
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defm : subvec_zero_lowering<"APS", VR128, v8f32, v4f32, sub_xmm>;
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defm : subvec_zero_lowering<"DQA", VR128, v4i64, v2i64, sub_xmm>;
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defm : subvec_zero_lowering<"DQA", VR128, v8i32, v4i32, sub_xmm>;
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defm : subvec_zero_lowering<"DQA", VR128, v16i16, v8i16, sub_xmm>;
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defm : subvec_zero_lowering<"DQA", VR128, v32i8, v16i8, sub_xmm>;
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}
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let Predicates = [HasAVXNECONVERT, NoVLX] in
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defm : subvec_zero_lowering<"DQA", VR128, v16bf16, v8bf16, sub_xmm>;
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let Predicates = [HasVLX] in {
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defm : subvec_zero_lowering<"APDZ128", VR128X, v4f64, v2f64, sub_xmm>;
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defm : subvec_zero_lowering<"APSZ128", VR128X, v8f32, v4f32, sub_xmm>;
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defm : subvec_zero_lowering<"DQA64Z128", VR128X, v4i64, v2i64, sub_xmm>;
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defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i32, v4i32, sub_xmm>;
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defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i16, v8i16, sub_xmm>;
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defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i8, v16i8, sub_xmm>;
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defm : subvec_zero_lowering<"APDZ128", VR128X, v8f64, v2f64, sub_xmm>;
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defm : subvec_zero_lowering<"APSZ128", VR128X, v16f32, v4f32, sub_xmm>;
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defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, sub_xmm>;
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defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i32, v4i32, sub_xmm>;
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defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i16, v8i16, sub_xmm>;
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defm : subvec_zero_lowering<"DQA64Z128", VR128X, v64i8, v16i8, sub_xmm>;
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defm : subvec_zero_lowering<"APDZ256", VR256X, v8f64, v4f64, sub_ymm>;
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defm : subvec_zero_lowering<"APSZ256", VR256X, v16f32, v8f32, sub_ymm>;
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defm : subvec_zero_lowering<"DQA64Z256", VR256X, v8i64, v4i64, sub_ymm>;
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defm : subvec_zero_lowering<"DQA64Z256", VR256X, v16i32, v8i32, sub_ymm>;
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defm : subvec_zero_lowering<"DQA64Z256", VR256X, v32i16, v16i16, sub_ymm>;
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defm : subvec_zero_lowering<"DQA64Z256", VR256X, v64i8, v32i8, sub_ymm>;
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}
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let Predicates = [HasAVX512, NoVLX] in {
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defm : subvec_zero_lowering<"APD", VR128, v8f64, v2f64, sub_xmm>;
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defm : subvec_zero_lowering<"APS", VR128, v16f32, v4f32, sub_xmm>;
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defm : subvec_zero_lowering<"DQA", VR128, v8i64, v2i64, sub_xmm>;
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defm : subvec_zero_lowering<"DQA", VR128, v16i32, v4i32, sub_xmm>;
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defm : subvec_zero_lowering<"DQA", VR128, v32i16, v8i16, sub_xmm>;
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defm : subvec_zero_lowering<"DQA", VR128, v64i8, v16i8, sub_xmm>;
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defm : subvec_zero_lowering<"APDY", VR256, v8f64, v4f64, sub_ymm>;
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defm : subvec_zero_lowering<"APSY", VR256, v16f32, v8f32, sub_ymm>;
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defm : subvec_zero_lowering<"DQAY", VR256, v8i64, v4i64, sub_ymm>;
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defm : subvec_zero_lowering<"DQAY", VR256, v16i32, v8i32, sub_ymm>;
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defm : subvec_zero_lowering<"DQAY", VR256, v32i16, v16i16, sub_ymm>;
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defm : subvec_zero_lowering<"DQAY", VR256, v64i8, v32i8, sub_ymm>;
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}
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let Predicates = [HasFP16, HasVLX] in {
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defm : subvec_zero_lowering<"APSZ128", VR128X, v16f16, v8f16, sub_xmm>;
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defm : subvec_zero_lowering<"APSZ128", VR128X, v32f16, v8f16, sub_xmm>;
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defm : subvec_zero_lowering<"APSZ256", VR256X, v32f16, v16f16, sub_ymm>;
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}
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let Predicates = [HasBF16, HasVLX] in {
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defm : subvec_zero_lowering<"APSZ128", VR128X, v16bf16, v8bf16, sub_xmm>;
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defm : subvec_zero_lowering<"APSZ128", VR128X, v32bf16, v8bf16, sub_xmm>;
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defm : subvec_zero_lowering<"APSZ256", VR256X, v32bf16, v16bf16, sub_ymm>;
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}
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class maskzeroupper<ValueType vt, RegisterClass RC> :
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PatLeaf<(vt RC:$src), [{
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return isMaskZeroExtended(N);
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}]>;
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def maskzeroupperv1i1 : maskzeroupper<v1i1, VK1>;
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def maskzeroupperv2i1 : maskzeroupper<v2i1, VK2>;
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def maskzeroupperv4i1 : maskzeroupper<v4i1, VK4>;
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def maskzeroupperv8i1 : maskzeroupper<v8i1, VK8>;
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def maskzeroupperv16i1 : maskzeroupper<v16i1, VK16>;
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def maskzeroupperv32i1 : maskzeroupper<v32i1, VK32>;
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// The patterns determine if we can depend on the upper bits of a mask register
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// being zeroed by the previous operation so that we can skip explicit
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// zeroing.
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let Predicates = [HasBWI] in {
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def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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maskzeroupperv1i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK1:$src, VK32)>;
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def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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maskzeroupperv8i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK8:$src, VK32)>;
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def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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maskzeroupperv16i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK16:$src, VK32)>;
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def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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maskzeroupperv1i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK1:$src, VK64)>;
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def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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maskzeroupperv8i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK8:$src, VK64)>;
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def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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maskzeroupperv16i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK16:$src, VK64)>;
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def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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maskzeroupperv32i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK32:$src, VK64)>;
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}
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let Predicates = [HasAVX512] in {
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def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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maskzeroupperv1i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK1:$src, VK16)>;
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def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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maskzeroupperv8i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK8:$src, VK16)>;
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}
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let Predicates = [HasDQI] in {
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def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
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maskzeroupperv1i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK1:$src, VK8)>;
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}
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let Predicates = [HasVLX, HasDQI] in {
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def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
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maskzeroupperv2i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK2:$src, VK8)>;
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def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
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maskzeroupperv4i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK4:$src, VK8)>;
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}
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let Predicates = [HasVLX] in {
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def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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maskzeroupperv2i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK2:$src, VK16)>;
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def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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maskzeroupperv4i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK4:$src, VK16)>;
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}
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let Predicates = [HasBWI, HasVLX] in {
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def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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maskzeroupperv2i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK2:$src, VK32)>;
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def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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maskzeroupperv4i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK4:$src, VK32)>;
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def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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maskzeroupperv2i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK2:$src, VK64)>;
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def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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maskzeroupperv4i1:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK4:$src, VK64)>;
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}
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// If the bits are not zero we have to fall back to explicitly zeroing by
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// using shifts.
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let Predicates = [HasAVX512] in {
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def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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(v1i1 VK1:$mask), (iPTR 0))),
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(KSHIFTRWki (KSHIFTLWki (COPY_TO_REGCLASS VK1:$mask, VK16),
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(i8 15)), (i8 15))>;
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def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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(v2i1 VK2:$mask), (iPTR 0))),
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(KSHIFTRWki (KSHIFTLWki (COPY_TO_REGCLASS VK2:$mask, VK16),
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(i8 14)), (i8 14))>;
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def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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(v4i1 VK4:$mask), (iPTR 0))),
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(KSHIFTRWki (KSHIFTLWki (COPY_TO_REGCLASS VK4:$mask, VK16),
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(i8 12)), (i8 12))>;
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}
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let Predicates = [HasAVX512, NoDQI] in {
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def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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(v8i1 VK8:$mask), (iPTR 0))),
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(KSHIFTRWki (KSHIFTLWki (COPY_TO_REGCLASS VK8:$mask, VK16),
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(i8 8)), (i8 8))>;
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}
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let Predicates = [HasDQI] in {
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def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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(v8i1 VK8:$mask), (iPTR 0))),
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(COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK16)>;
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def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
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(v1i1 VK1:$mask), (iPTR 0))),
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(KSHIFTRBki (KSHIFTLBki (COPY_TO_REGCLASS VK1:$mask, VK8),
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(i8 7)), (i8 7))>;
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def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
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(v2i1 VK2:$mask), (iPTR 0))),
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(KSHIFTRBki (KSHIFTLBki (COPY_TO_REGCLASS VK2:$mask, VK8),
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(i8 6)), (i8 6))>;
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def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
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(v4i1 VK4:$mask), (iPTR 0))),
|
|
(KSHIFTRBki (KSHIFTLBki (COPY_TO_REGCLASS VK4:$mask, VK8),
|
|
(i8 4)), (i8 4))>;
|
|
}
|
|
|
|
let Predicates = [HasBWI] in {
|
|
def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
|
|
(v16i1 VK16:$mask), (iPTR 0))),
|
|
(COPY_TO_REGCLASS (KMOVWkk VK16:$mask), VK32)>;
|
|
|
|
def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
|
|
(v16i1 VK16:$mask), (iPTR 0))),
|
|
(COPY_TO_REGCLASS (KMOVWkk VK16:$mask), VK64)>;
|
|
def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
|
|
(v32i1 VK32:$mask), (iPTR 0))),
|
|
(COPY_TO_REGCLASS (KMOVDkk VK32:$mask), VK64)>;
|
|
}
|
|
|
|
let Predicates = [HasBWI, NoDQI] in {
|
|
def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
|
|
(v8i1 VK8:$mask), (iPTR 0))),
|
|
(KSHIFTRDki (KSHIFTLDki (COPY_TO_REGCLASS VK8:$mask, VK32),
|
|
(i8 24)), (i8 24))>;
|
|
|
|
def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
|
|
(v8i1 VK8:$mask), (iPTR 0))),
|
|
(KSHIFTRQki (KSHIFTLQki (COPY_TO_REGCLASS VK8:$mask, VK64),
|
|
(i8 56)), (i8 56))>;
|
|
}
|
|
|
|
let Predicates = [HasBWI, HasDQI] in {
|
|
def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
|
|
(v8i1 VK8:$mask), (iPTR 0))),
|
|
(COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK32)>;
|
|
|
|
def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
|
|
(v8i1 VK8:$mask), (iPTR 0))),
|
|
(COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK64)>;
|
|
}
|
|
|
|
let Predicates = [HasBWI] in {
|
|
def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
|
|
(v1i1 VK1:$mask), (iPTR 0))),
|
|
(KSHIFTRDki (KSHIFTLDki (COPY_TO_REGCLASS VK1:$mask, VK32),
|
|
(i8 31)), (i8 31))>;
|
|
def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
|
|
(v2i1 VK2:$mask), (iPTR 0))),
|
|
(KSHIFTRDki (KSHIFTLDki (COPY_TO_REGCLASS VK2:$mask, VK32),
|
|
(i8 30)), (i8 30))>;
|
|
def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
|
|
(v4i1 VK4:$mask), (iPTR 0))),
|
|
(KSHIFTRDki (KSHIFTLDki (COPY_TO_REGCLASS VK4:$mask, VK32),
|
|
(i8 28)), (i8 28))>;
|
|
|
|
def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
|
|
(v1i1 VK1:$mask), (iPTR 0))),
|
|
(KSHIFTRQki (KSHIFTLQki (COPY_TO_REGCLASS VK1:$mask, VK64),
|
|
(i8 63)), (i8 63))>;
|
|
def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
|
|
(v2i1 VK2:$mask), (iPTR 0))),
|
|
(KSHIFTRQki (KSHIFTLQki (COPY_TO_REGCLASS VK2:$mask, VK64),
|
|
(i8 62)), (i8 62))>;
|
|
def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
|
|
(v4i1 VK4:$mask), (iPTR 0))),
|
|
(KSHIFTRQki (KSHIFTLQki (COPY_TO_REGCLASS VK4:$mask, VK64),
|
|
(i8 60)), (i8 60))>;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Extra selection patterns for f128, f128mem
|
|
|
|
// movaps is shorter than movdqa. movaps is in SSE and movdqa is in SSE2.
|
|
let Predicates = [NoAVX] in {
|
|
def : Pat<(alignedstore (f128 VR128:$src), addr:$dst),
|
|
(MOVAPSmr addr:$dst, VR128:$src)>;
|
|
def : Pat<(store (f128 VR128:$src), addr:$dst),
|
|
(MOVUPSmr addr:$dst, VR128:$src)>;
|
|
|
|
def : Pat<(alignedloadf128 addr:$src),
|
|
(MOVAPSrm addr:$src)>;
|
|
def : Pat<(loadf128 addr:$src),
|
|
(MOVUPSrm addr:$src)>;
|
|
}
|
|
|
|
let Predicates = [HasAVX, NoVLX] in {
|
|
def : Pat<(alignedstore (f128 VR128:$src), addr:$dst),
|
|
(VMOVAPSmr addr:$dst, VR128:$src)>;
|
|
def : Pat<(store (f128 VR128:$src), addr:$dst),
|
|
(VMOVUPSmr addr:$dst, VR128:$src)>;
|
|
|
|
def : Pat<(alignedloadf128 addr:$src),
|
|
(VMOVAPSrm addr:$src)>;
|
|
def : Pat<(loadf128 addr:$src),
|
|
(VMOVUPSrm addr:$src)>;
|
|
}
|
|
|
|
let Predicates = [HasVLX] in {
|
|
def : Pat<(alignedstore (f128 VR128X:$src), addr:$dst),
|
|
(VMOVAPSZ128mr addr:$dst, VR128X:$src)>;
|
|
def : Pat<(store (f128 VR128X:$src), addr:$dst),
|
|
(VMOVUPSZ128mr addr:$dst, VR128X:$src)>;
|
|
|
|
def : Pat<(alignedloadf128 addr:$src),
|
|
(VMOVAPSZ128rm addr:$src)>;
|
|
def : Pat<(loadf128 addr:$src),
|
|
(VMOVUPSZ128rm addr:$src)>;
|
|
}
|
|
|
|
let Predicates = [UseSSE1] in {
|
|
// andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
|
|
def : Pat<(f128 (X86fand VR128:$src1, (memopf128 addr:$src2))),
|
|
(ANDPSrm VR128:$src1, f128mem:$src2)>;
|
|
|
|
def : Pat<(f128 (X86fand VR128:$src1, VR128:$src2)),
|
|
(ANDPSrr VR128:$src1, VR128:$src2)>;
|
|
|
|
def : Pat<(f128 (X86for VR128:$src1, (memopf128 addr:$src2))),
|
|
(ORPSrm VR128:$src1, f128mem:$src2)>;
|
|
|
|
def : Pat<(f128 (X86for VR128:$src1, VR128:$src2)),
|
|
(ORPSrr VR128:$src1, VR128:$src2)>;
|
|
|
|
def : Pat<(f128 (X86fxor VR128:$src1, (memopf128 addr:$src2))),
|
|
(XORPSrm VR128:$src1, f128mem:$src2)>;
|
|
|
|
def : Pat<(f128 (X86fxor VR128:$src1, VR128:$src2)),
|
|
(XORPSrr VR128:$src1, VR128:$src2)>;
|
|
}
|
|
|
|
let Predicates = [HasAVX, NoVLX] in {
|
|
// andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
|
|
def : Pat<(f128 (X86fand VR128:$src1, (loadf128 addr:$src2))),
|
|
(VANDPSrm VR128:$src1, f128mem:$src2)>;
|
|
|
|
def : Pat<(f128 (X86fand VR128:$src1, VR128:$src2)),
|
|
(VANDPSrr VR128:$src1, VR128:$src2)>;
|
|
|
|
def : Pat<(f128 (X86for VR128:$src1, (loadf128 addr:$src2))),
|
|
(VORPSrm VR128:$src1, f128mem:$src2)>;
|
|
|
|
def : Pat<(f128 (X86for VR128:$src1, VR128:$src2)),
|
|
(VORPSrr VR128:$src1, VR128:$src2)>;
|
|
|
|
def : Pat<(f128 (X86fxor VR128:$src1, (loadf128 addr:$src2))),
|
|
(VXORPSrm VR128:$src1, f128mem:$src2)>;
|
|
|
|
def : Pat<(f128 (X86fxor VR128:$src1, VR128:$src2)),
|
|
(VXORPSrr VR128:$src1, VR128:$src2)>;
|
|
}
|
|
|
|
let Predicates = [HasVLX] in {
|
|
// andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
|
|
def : Pat<(f128 (X86fand VR128X:$src1, (loadf128 addr:$src2))),
|
|
(VANDPSZ128rm VR128X:$src1, f128mem:$src2)>;
|
|
|
|
def : Pat<(f128 (X86fand VR128X:$src1, VR128X:$src2)),
|
|
(VANDPSZ128rr VR128X:$src1, VR128X:$src2)>;
|
|
|
|
def : Pat<(f128 (X86for VR128X:$src1, (loadf128 addr:$src2))),
|
|
(VORPSZ128rm VR128X:$src1, f128mem:$src2)>;
|
|
|
|
def : Pat<(f128 (X86for VR128X:$src1, VR128X:$src2)),
|
|
(VORPSZ128rr VR128X:$src1, VR128X:$src2)>;
|
|
|
|
def : Pat<(f128 (X86fxor VR128X:$src1, (loadf128 addr:$src2))),
|
|
(VXORPSZ128rm VR128X:$src1, f128mem:$src2)>;
|
|
|
|
def : Pat<(f128 (X86fxor VR128X:$src1, VR128X:$src2)),
|
|
(VXORPSZ128rr VR128X:$src1, VR128X:$src2)>;
|
|
}
|