3ffaaf6db6
Implement Xtensa S32C1I Option. Implement atomic_cmp_swap_32 operation using s32c1i instruction. Use atomic_cmp_swap_32 operation and AtomicExpand pass to implement atomics operations.
105 lines
4.1 KiB
C++
105 lines
4.1 KiB
C++
//===-- XtensaSubtarget.h - Define Subtarget for the Xtensa ----*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the Xtensa specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_XTENSA_XTENSASUBTARGET_H
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#define LLVM_LIB_TARGET_XTENSA_XTENSASUBTARGET_H
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#include "XtensaFrameLowering.h"
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#include "XtensaISelLowering.h"
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#include "XtensaInstrInfo.h"
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#include "XtensaRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetMachine.h"
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#define GET_SUBTARGETINFO_HEADER
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#include "XtensaGenSubtargetInfo.inc"
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namespace llvm {
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class StringRef;
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class XtensaSubtarget : public XtensaGenSubtargetInfo {
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private:
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// Bool members corresponding to the SubtargetFeatures defined in tablegen
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#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
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bool ATTRIBUTE = DEFAULT;
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#include "XtensaGenSubtargetInfo.inc"
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const Triple &TargetTriple;
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XtensaInstrInfo InstrInfo;
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XtensaTargetLowering TLInfo;
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SelectionDAGTargetInfo TSInfo;
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XtensaFrameLowering FrameLowering;
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XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
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public:
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XtensaSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
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const TargetMachine &TM);
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const Triple &getTargetTriple() const { return TargetTriple; }
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const TargetFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const XtensaInstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const XtensaRegisterInfo *getRegisterInfo() const override {
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return &InstrInfo.getRegisterInfo();
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}
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const XtensaTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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bool hasDensity() const { return HasDensity; }
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bool hasMAC16() const { return HasMAC16; }
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bool hasWindowed() const { return HasWindowed; }
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bool hasBoolean() const { return HasBoolean; }
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bool hasLoop() const { return HasLoop; }
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bool hasSEXT() const { return HasSEXT; }
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bool hasCLAMPS() const { return HasCLAMPS; }
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bool hasNSA() const { return HasNSA; }
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bool hasMINMAX() const { return HasMINMAX; }
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bool hasMul16() const { return HasMul16; }
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bool hasMul32() const { return HasMul32; }
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bool hasMul32High() const { return HasMul32High; }
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bool hasDiv32() const { return HasDiv32; }
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bool hasS32C1I() const { return HasS32C1I; }
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bool hasForcedAtomics() const { return HasForcedAtomics; }
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bool hasSingleFloat() const { return HasSingleFloat; }
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bool hasRegionProtection() const { return HasRegionProtection; }
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bool hasRelocatableVector() const { return HasRelocatableVector; }
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bool hasMiscSR() const { return HasMiscSR; }
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bool hasExtendedL32R() const { return HasExtendedL32R; }
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bool hasDataCache() const { return HasDataCache; }
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bool hasHighPriInterrupts() const { return HasHighPriInterrupts; }
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bool hasHighPriInterruptsLevel3() const { return HasHighPriInterruptsLevel3; }
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bool hasHighPriInterruptsLevel4() const { return HasHighPriInterruptsLevel4; }
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bool hasHighPriInterruptsLevel5() const { return HasHighPriInterruptsLevel5; }
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bool hasHighPriInterruptsLevel6() const { return HasHighPriInterruptsLevel6; }
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bool hasHighPriInterruptsLevel7() const { return HasHighPriInterruptsLevel7; }
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bool hasInterrupt() const { return HasInterrupt; }
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bool hasException() const { return HasException; }
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bool hasTHREADPTR() const { return HasTHREADPTR; }
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bool isWindowedABI() const { return hasWindowed(); }
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// Automatically generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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};
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} // end namespace llvm
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#endif /* LLVM_LIB_TARGET_XTENSA_XTENSASUBTARGET_H */
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