db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
20 lines
704 B
LLVM
20 lines
704 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -mcpu=cortex-a57 -aarch64-enable-early-ifcvt=false | FileCheck %s
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; Check that the select isn't expanded into a branch sequence
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; when the icmp's first operand %x0 is from load.
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define i64 @f(i64 %a, i64 %b, ptr %c, i64 %d, i64 %e) {
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; CHECK-LABEL: f:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr x8, [x2]
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; CHECK-NEXT: cmp x8, #0
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; CHECK-NEXT: csel x8, x0, x1, eq
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; CHECK-NEXT: add x0, x8, x3
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; CHECK-NEXT: ret
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%x0 = load i64, ptr %c
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%x1 = icmp eq i64 %x0, 0
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%x2 = select i1 %x1, i64 %a, i64 %b
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%x3 = add i64 %x2, %d
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ret i64 %x3
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}
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