2ec91a5ec4
This is essentially from performAddSubCombine. addsub.ll has been cleaned up a little in the process.
169 lines
4.9 KiB
LLVM
169 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=aarch64-none-elf -mattr=+aes < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64-none-elf -mattr=+aes -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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define i64 @add_i64_ext_load(<1 x i64> %A, ptr %B) nounwind {
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; CHECK-SD-LABEL: add_i64_ext_load:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: ldr d1, [x0]
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; CHECK-SD-NEXT: add d0, d0, d1
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; CHECK-SD-NEXT: fmov x0, d0
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: add_i64_ext_load:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: fmov x9, d0
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; CHECK-GI-NEXT: ldr x8, [x0]
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; CHECK-GI-NEXT: add x0, x9, x8
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; CHECK-GI-NEXT: ret
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%a = extractelement <1 x i64> %A, i32 0
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%b = load i64, ptr %B
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%c = add i64 %a, %b
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ret i64 %c
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}
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define i64 @sub_i64_ext_load(<1 x i64> %A, ptr %B) nounwind {
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; CHECK-SD-LABEL: sub_i64_ext_load:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: ldr d1, [x0]
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; CHECK-SD-NEXT: sub d0, d0, d1
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; CHECK-SD-NEXT: fmov x0, d0
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: sub_i64_ext_load:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: fmov x9, d0
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; CHECK-GI-NEXT: ldr x8, [x0]
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; CHECK-GI-NEXT: sub x0, x9, x8
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; CHECK-GI-NEXT: ret
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%a = extractelement <1 x i64> %A, i32 0
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%b = load i64, ptr %B
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%c = sub i64 %a, %b
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ret i64 %c
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}
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define void @add_i64_ext_load_store(<1 x i64> %A, ptr %B) nounwind {
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; CHECK-SD-LABEL: add_i64_ext_load_store:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: ldr d1, [x0]
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; CHECK-SD-NEXT: add d0, d0, d1
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; CHECK-SD-NEXT: str d0, [x0]
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: add_i64_ext_load_store:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: fmov x9, d0
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; CHECK-GI-NEXT: ldr x8, [x0]
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; CHECK-GI-NEXT: add x8, x9, x8
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; CHECK-GI-NEXT: str x8, [x0]
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; CHECK-GI-NEXT: ret
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%a = extractelement <1 x i64> %A, i32 0
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%b = load i64, ptr %B
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%c = add i64 %a, %b
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store i64 %c, ptr %B
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ret void
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}
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define i64 @add_v2i64_ext_load(<2 x i64> %A, ptr %B) nounwind {
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; CHECK-LABEL: add_v2i64_ext_load:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: ldr x8, [x0]
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; CHECK-NEXT: add x0, x9, x8
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; CHECK-NEXT: ret
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%a = extractelement <2 x i64> %A, i32 0
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%b = load i64, ptr %B
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%c = add i64 %a, %b
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ret i64 %c
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}
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define i64 @add_i64_ext_ext(<1 x i64> %A, <1 x i64> %B) nounwind {
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; CHECK-SD-LABEL: add_i64_ext_ext:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: add d0, d0, d1
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; CHECK-SD-NEXT: fmov x0, d0
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: add_i64_ext_ext:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: fmov x8, d0
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; CHECK-GI-NEXT: fmov x9, d1
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; CHECK-GI-NEXT: add x0, x8, x9
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; CHECK-GI-NEXT: ret
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%a = extractelement <1 x i64> %A, i32 0
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%b = extractelement <1 x i64> %B, i32 0
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%c = add i64 %a, %b
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ret i64 %c
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}
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define i32 @add_i32_ext_load(<1 x i32> %A, ptr %B) nounwind {
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; CHECK-SD-LABEL: add_i32_ext_load:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-SD-NEXT: fmov w9, s0
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; CHECK-SD-NEXT: ldr w8, [x0]
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; CHECK-SD-NEXT: add w0, w9, w8
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: add_i32_ext_load:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: fmov w9, s0
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; CHECK-GI-NEXT: ldr w8, [x0]
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; CHECK-GI-NEXT: add w0, w9, w8
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; CHECK-GI-NEXT: ret
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%a = extractelement <1 x i32> %A, i32 0
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%b = load i32, ptr %B
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%c = add i32 %a, %b
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ret i32 %c
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}
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define i64 @add_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
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; CHECK-SD-LABEL: add_i64_ext_ext_test1:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: ext v2.16b, v1.16b, v1.16b, #8
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; CHECK-SD-NEXT: add d0, d0, d1
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; CHECK-SD-NEXT: add d0, d0, d2
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; CHECK-SD-NEXT: fmov x0, d0
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: add_i64_ext_ext_test1:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov x8, v1.d[1]
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; CHECK-GI-NEXT: fmov x9, d0
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; CHECK-GI-NEXT: fmov x10, d1
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; CHECK-GI-NEXT: add x9, x9, x10
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; CHECK-GI-NEXT: add x0, x9, x8
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; CHECK-GI-NEXT: ret
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%a = extractelement <1 x i64> %A, i32 0
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%b = extractelement <2 x i64> %B, i32 0
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%c = extractelement <2 x i64> %B, i32 1
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%d = add i64 %a, %b
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%e = add i64 %d, %c
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ret i64 %e
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}
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define i64 @sub_i64_ext_ext_test1(<1 x i64> %A, <2 x i64> %B) nounwind {
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; CHECK-SD-LABEL: sub_i64_ext_ext_test1:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: ext v2.16b, v1.16b, v1.16b, #8
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; CHECK-SD-NEXT: sub d0, d0, d1
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; CHECK-SD-NEXT: sub d0, d0, d2
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; CHECK-SD-NEXT: fmov x0, d0
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: sub_i64_ext_ext_test1:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov x8, v1.d[1]
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; CHECK-GI-NEXT: fmov x9, d0
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; CHECK-GI-NEXT: fmov x10, d1
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; CHECK-GI-NEXT: sub x9, x9, x10
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; CHECK-GI-NEXT: sub x0, x9, x8
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; CHECK-GI-NEXT: ret
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%a = extractelement <1 x i64> %A, i32 0
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%b = extractelement <2 x i64> %B, i32 0
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%c = extractelement <2 x i64> %B, i32 1
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%d = sub i64 %a, %b
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%e = sub i64 %d, %c
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ret i64 %e
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}
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