7e2f96194f
4e0bd3f improved early MachineLICM's capabilities to hoist COPY from physical registers out of a loop. However, it accidentally broke one of MachineSink's preconditions on sinking cheap instructions (in this case, COPY) which considered those instructions being profitable to sink only when there are at least two of them in the same def-use chain in the same basic block. So if early MachineLICM hoisted one of them out, MachineSink no longer sink rest of the cheap instructions. This results in redundant load immediate instructions from the motivating example we've seen on RISC-V. This patch fixes this by teaching MachineSink that if there is more than one demand to sink a register into the same block from different critical edges, it should be considered profitable as it increases the CSE opportunities. This change also improves two of the AArch64's cases.
123 lines
3.5 KiB
LLVM
123 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs < %s | FileCheck %s
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; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -mtriple=aarch64-linux %s | FileCheck --check-prefix=CHECK-CGP %s
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; RUN: opt -S -passes='require<profile-summary>,function(codegenprepare)' -cgpp-huge-func=0 -mtriple=aarch64-linux %s | FileCheck --check-prefix=CHECK-CGP %s
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@A = dso_local global i32 zeroinitializer
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@B = dso_local global i32 zeroinitializer
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@C = dso_local global i32 zeroinitializer
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; Test that and is sunk into cmp block to form tbz.
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define dso_local i32 @and_sink1(i32 %a, i1 %c) {
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; CHECK-LABEL: and_sink1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tbz w1, #0, .LBB0_3
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; CHECK-NEXT: // %bb.1: // %bb0
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; CHECK-NEXT: adrp x8, A
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; CHECK-NEXT: str wzr, [x8, :lo12:A]
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; CHECK-NEXT: tbnz w0, #2, .LBB0_3
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; CHECK-NEXT: // %bb.2:
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; CHECK-NEXT: mov w0, #1 // =0x1
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_3: // %bb2
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-CGP-LABEL: @and_sink1(
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; CHECK-CGP-NOT: and i32
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%and = and i32 %a, 4
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br i1 %c, label %bb0, label %bb2
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bb0:
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; CHECK-CGP-LABEL: bb0:
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; CHECK-CGP: and i32
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; CHECK-CGP-NEXT: icmp eq i32
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; CHECK-CGP-NEXT: store
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; CHECK-CGP-NEXT: br
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%cmp = icmp eq i32 %and, 0
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store i32 0, ptr @A
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br i1 %cmp, label %bb1, label %bb2
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bb1:
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ret i32 1
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bb2:
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ret i32 0
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}
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; Test that both 'and' and cmp get sunk to form tbz.
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define dso_local i32 @and_sink2(i32 %a, i1 %c, i1 %c2) {
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; CHECK-LABEL: and_sink2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, A
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; CHECK-NEXT: str wzr, [x8, :lo12:A]
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; CHECK-NEXT: tbz w1, #0, .LBB1_5
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; CHECK-NEXT: // %bb.1: // %bb0.preheader
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; CHECK-NEXT: adrp x8, B
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; CHECK-NEXT: adrp x9, C
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; CHECK-NEXT: .LBB1_2: // %bb0
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: str wzr, [x8, :lo12:B]
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; CHECK-NEXT: tbz w2, #0, .LBB1_5
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; CHECK-NEXT: // %bb.3: // %bb1
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: str wzr, [x9, :lo12:C]
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; CHECK-NEXT: tbnz w0, #2, .LBB1_2
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; CHECK-NEXT: // %bb.4:
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; CHECK-NEXT: mov w0, #1 // =0x1
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB1_5:
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-CGP-LABEL: @and_sink2(
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; CHECK-CGP-NOT: and i32
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%and = and i32 %a, 4
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store i32 0, ptr @A
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br i1 %c, label %bb0, label %bb3
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bb0:
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; CHECK-CGP-LABEL: bb0:
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; CHECK-CGP-NOT: and i32
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; CHECK-CGP-NOT: icmp
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%cmp = icmp eq i32 %and, 0
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store i32 0, ptr @B
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br i1 %c2, label %bb1, label %bb3
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bb1:
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; CHECK-CGP-LABEL: bb1:
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; CHECK-CGP: and i32
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; CHECK-CGP-NEXT: icmp eq i32
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; CHECK-CGP-NEXT: store
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; CHECK-CGP-NEXT: br
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store i32 0, ptr @C
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br i1 %cmp, label %bb2, label %bb0
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bb2:
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ret i32 1
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bb3:
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ret i32 0
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}
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; Test that 'and' is not sunk since cbz is a better alternative.
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define dso_local i32 @and_sink3(i32 %a) {
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; CHECK-LABEL: and_sink3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, A
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; CHECK-NEXT: and w9, w0, #0x3
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; CHECK-NEXT: .LBB2_1: // %bb0
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: str wzr, [x8, :lo12:A]
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; CHECK-NEXT: cbz w9, .LBB2_1
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; CHECK-NEXT: // %bb.2: // %bb2
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; CHECK-NEXT: mov w0, wzr
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; CHECK-NEXT: ret
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; CHECK-CGP-LABEL: @and_sink3(
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; CHECK-CGP-NEXT: and i32
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%and = and i32 %a, 3
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br label %bb0
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bb0:
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; CHECK-CGP-LABEL: bb0:
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; CHECK-CGP-NOT: and i32
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%cmp = icmp eq i32 %and, 0
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store i32 0, ptr @A
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br i1 %cmp, label %bb0, label %bb2
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bb2:
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ret i32 0
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}
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