048fc2bc10
If parts of a physical register for a given liverange, as assigned by the register allocator, can be used to store other values not represented by this liverange, then `LiveIntervals::addKillFlags` normally avoids adding a kill flag on the use of this register when the value's liverange ends. However, if all the other regunits are artificial, then we can still safely add the kill flag, since those parts of the register can never be accessed independently.
542 lines
15 KiB
LLVM
542 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -aarch64-enable-subreg-liveness-tracking -mtriple=arm64-eabi < %s | FileCheck %s
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; rdar://10232252
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@object = external hidden global i64, section "__DATA, __objc_ivar", align 8
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; base + offset (imm9)
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define void @t1(ptr %object) {
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; CHECK-LABEL: t1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr xzr, [x0, #8]
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; CHECK-NEXT: ret
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%incdec.ptr = getelementptr inbounds i64, ptr %object, i64 1
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%tmp = load volatile i64, ptr %incdec.ptr, align 8
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ret void
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}
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; base + offset (> imm9)
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define void @t2(ptr %object) {
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; CHECK-LABEL: t2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub x8, x0, #264
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; CHECK-NEXT: ldr xzr, [x8]
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; CHECK-NEXT: ret
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%incdec.ptr = getelementptr inbounds i64, ptr %object, i64 -33
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%tmp = load volatile i64, ptr %incdec.ptr, align 8
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ret void
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}
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; base + unsigned offset (> imm9 and <= imm12 * size of type in bytes)
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define void @t3(ptr %object) {
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; CHECK-LABEL: t3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr xzr, [x0, #32760]
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; CHECK-NEXT: ret
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%incdec.ptr = getelementptr inbounds i64, ptr %object, i64 4095
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%tmp = load volatile i64, ptr %incdec.ptr, align 8
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ret void
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}
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; base + unsigned offset (> imm12 * size of type in bytes)
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define void @t4(ptr %object) {
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; CHECK-LABEL: t4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #32768 // =0x8000
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; CHECK-NEXT: ldr xzr, [x0, x8]
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; CHECK-NEXT: ret
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%incdec.ptr = getelementptr inbounds i64, ptr %object, i64 4096
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%tmp = load volatile i64, ptr %incdec.ptr, align 8
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ret void
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}
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; base + reg
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define void @t5(i64 %a) {
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; CHECK-LABEL: t5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, object
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; CHECK-NEXT: add x8, x8, :lo12:object
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; CHECK-NEXT: ldr xzr, [x8, x0, lsl #3]
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; CHECK-NEXT: ret
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%incdec.ptr = getelementptr inbounds i64, ptr @object, i64 %a
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%tmp = load volatile i64, ptr %incdec.ptr, align 8
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ret void
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}
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; base + reg + imm
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define void @t6(i64 %a, ptr %object) {
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; CHECK-LABEL: t6:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x1, x0, lsl #3
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; CHECK-NEXT: mov w9, #32768 // =0x8000
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; CHECK-NEXT: ldr xzr, [x8, x9]
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; CHECK-NEXT: ret
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%tmp1 = getelementptr inbounds i64, ptr %object, i64 %a
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%incdec.ptr = getelementptr inbounds i64, ptr %tmp1, i64 4096
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%tmp = load volatile i64, ptr %incdec.ptr, align 8
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ret void
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}
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; Test base + wide immediate
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define void @t7(i64 %a) {
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; CHECK-LABEL: t7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #65535 // =0xffff
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; CHECK-NEXT: ldr xzr, [x0, x8]
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; CHECK-NEXT: ret
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%1 = add i64 %a, 65535 ;0xffff
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%2 = inttoptr i64 %1 to ptr
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%3 = load volatile i64, ptr %2, align 8
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ret void
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}
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define void @t8(i64 %a) {
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; CHECK-LABEL: t8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #-4662 // =0xffffffffffffedca
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; CHECK-NEXT: ldr xzr, [x0, x8]
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; CHECK-NEXT: ret
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%1 = sub i64 %a, 4662 ;-4662 is 0xffffffffffffedca
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%2 = inttoptr i64 %1 to ptr
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%3 = load volatile i64, ptr %2, align 8
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ret void
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}
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define void @t9(i64 %a) {
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; CHECK-LABEL: t9:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #-305463297 // =0xffffffffedcaffff
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; CHECK-NEXT: ldr xzr, [x0, x8]
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; CHECK-NEXT: ret
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%1 = add i64 -305463297, %a ;-305463297 is 0xffffffffedcaffff
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%2 = inttoptr i64 %1 to ptr
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%3 = load volatile i64, ptr %2, align 8
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ret void
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}
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define void @t10(i64 %a) {
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; CHECK-LABEL: t10:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, #81909218222800896 // =0x123000000000000
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; CHECK-NEXT: ldr xzr, [x0, x8]
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; CHECK-NEXT: ret
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%1 = add i64 %a, 81909218222800896 ;0x123000000000000
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%2 = inttoptr i64 %1 to ptr
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%3 = load volatile i64, ptr %2, align 8
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ret void
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}
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define void @t11(i64 %a) {
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; CHECK-LABEL: t11:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #17767 // =0x4567
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; CHECK-NEXT: movk w8, #291, lsl #16
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; CHECK-NEXT: ldr xzr, [x0, x8]
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; CHECK-NEXT: ret
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%1 = add i64 %a, 19088743 ;0x1234567
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%2 = inttoptr i64 %1 to ptr
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%3 = load volatile i64, ptr %2, align 8
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ret void
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}
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; Test some boundaries that should not use movz/movn/orr
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define void @t12(i64 %a) {
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; CHECK-LABEL: t12:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #4095
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; CHECK-NEXT: ldr xzr, [x8]
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; CHECK-NEXT: ret
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%1 = add i64 %a, 4095 ;0xfff
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%2 = inttoptr i64 %1 to ptr
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%3 = load volatile i64, ptr %2, align 8
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ret void
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}
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define void @t13(i64 %a) {
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; CHECK-LABEL: t13:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub x8, x0, #4095
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; CHECK-NEXT: ldr xzr, [x8]
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; CHECK-NEXT: ret
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%1 = add i64 %a, -4095 ;-0xfff
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%2 = inttoptr i64 %1 to ptr
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%3 = load volatile i64, ptr %2, align 8
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ret void
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}
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define void @t14(i64 %a) {
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; CHECK-LABEL: t14:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #291, lsl #12 // =1191936
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; CHECK-NEXT: ldr xzr, [x8]
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; CHECK-NEXT: ret
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%1 = add i64 %a, 1191936 ;0x123000
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%2 = inttoptr i64 %1 to ptr
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%3 = load volatile i64, ptr %2, align 8
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ret void
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}
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define void @t15(i64 %a) {
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; CHECK-LABEL: t15:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub x8, x0, #291, lsl #12 // =1191936
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; CHECK-NEXT: ldr xzr, [x8]
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; CHECK-NEXT: ret
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%1 = add i64 %a, -1191936 ;0xFFFFFFFFFFEDD000
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%2 = inttoptr i64 %1 to ptr
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%3 = load volatile i64, ptr %2, align 8
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ret void
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}
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define void @t16(i64 %a) {
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; CHECK-LABEL: t16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr xzr, [x0, #28672]
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; CHECK-NEXT: ret
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%1 = add i64 %a, 28672 ;0x7000
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%2 = inttoptr i64 %1 to ptr
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%3 = load volatile i64, ptr %2, align 8
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ret void
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}
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define void @t17(i64 %a) {
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; CHECK-LABEL: t17:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldur xzr, [x0, #-256]
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; CHECK-NEXT: ret
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%1 = add i64 %a, -256 ;-0x100
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%2 = inttoptr i64 %1 to ptr
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%3 = load volatile i64, ptr %2, align 8
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ret void
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}
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; LDRBBroX
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define i8 @LdOffset_i8(ptr %a) {
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; CHECK-LABEL: LdOffset_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
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; CHECK-NEXT: ldrb w0, [x8, #3704]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
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%val = load i8, ptr %arrayidx, align 1
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ret i8 %val
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}
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; LDRBBroX
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define i32 @LdOffset_i8_zext32(ptr %a) {
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; CHECK-LABEL: LdOffset_i8_zext32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
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; CHECK-NEXT: ldrb w0, [x8, #3704]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
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%val = load i8, ptr %arrayidx, align 1
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%conv = zext i8 %val to i32
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ret i32 %conv
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}
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; LDRSBWroX
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define i32 @LdOffset_i8_sext32(ptr %a) {
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; CHECK-LABEL: LdOffset_i8_sext32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
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; CHECK-NEXT: ldrsb w0, [x8, #3704]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
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%val = load i8, ptr %arrayidx, align 1
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%conv = sext i8 %val to i32
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ret i32 %conv
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}
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; LDRBBroX
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define i64 @LdOffset_i8_zext64(ptr %a) {
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; CHECK-LABEL: LdOffset_i8_zext64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
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; CHECK-NEXT: ldrb w0, [x8, #3704]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
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%val = load i8, ptr %arrayidx, align 1
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%conv = zext i8 %val to i64
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ret i64 %conv
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}
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; LDRSBXroX
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define i64 @LdOffset_i8_sext64(ptr %a) {
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; CHECK-LABEL: LdOffset_i8_sext64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
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; CHECK-NEXT: ldrsb x0, [x8, #3704]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
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%val = load i8, ptr %arrayidx, align 1
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%conv = sext i8 %val to i64
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ret i64 %conv
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}
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; LDRHHroX
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define i16 @LdOffset_i16(ptr %a) {
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; CHECK-LABEL: LdOffset_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
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; CHECK-NEXT: ldrh w0, [x8, #7408]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
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%val = load i16, ptr %arrayidx, align 2
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ret i16 %val
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}
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; LDRHHroX
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define i32 @LdOffset_i16_zext32(ptr %a) {
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; CHECK-LABEL: LdOffset_i16_zext32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
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; CHECK-NEXT: ldrh w0, [x8, #7408]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
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%val = load i16, ptr %arrayidx, align 2
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%conv = zext i16 %val to i32
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ret i32 %conv
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}
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; LDRSHWroX
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define i32 @LdOffset_i16_sext32(ptr %a) {
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; CHECK-LABEL: LdOffset_i16_sext32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
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; CHECK-NEXT: ldrsh w0, [x8, #7408]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
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%val = load i16, ptr %arrayidx, align 2
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%conv = sext i16 %val to i32
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ret i32 %conv
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}
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; LDRHHroX
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define i64 @LdOffset_i16_zext64(ptr %a) {
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; CHECK-LABEL: LdOffset_i16_zext64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
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; CHECK-NEXT: ldrh w0, [x8, #7408]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
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%val = load i16, ptr %arrayidx, align 2
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%conv = zext i16 %val to i64
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ret i64 %conv
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}
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; LDRSHXroX
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define i64 @LdOffset_i16_sext64(ptr %a) {
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; CHECK-LABEL: LdOffset_i16_sext64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
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; CHECK-NEXT: ldrsh x0, [x8, #7408]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
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%val = load i16, ptr %arrayidx, align 2
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%conv = sext i16 %val to i64
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ret i64 %conv
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}
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; LDRWroX
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define i32 @LdOffset_i32(ptr %a) {
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; CHECK-LABEL: LdOffset_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
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; CHECK-NEXT: ldr w0, [x8, #14816]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
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%val = load i32, ptr %arrayidx, align 4
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ret i32 %val
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}
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; LDRWroX
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define i64 @LdOffset_i32_zext64(ptr %a) {
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; CHECK-LABEL: LdOffset_i32_zext64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
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; CHECK-NEXT: ldr w0, [x8, #14816]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
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%val = load i32, ptr %arrayidx, align 2
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%conv = zext i32 %val to i64
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ret i64 %conv
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}
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; LDRSWroX
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define i64 @LdOffset_i32_sext64(ptr %a) {
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; CHECK-LABEL: LdOffset_i32_sext64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
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; CHECK-NEXT: ldrsw x0, [x8, #14816]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
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%val = load i32, ptr %arrayidx, align 2
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%conv = sext i32 %val to i64
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ret i64 %conv
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}
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; LDRXroX
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define i64 @LdOffset_i64(ptr %a) {
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; CHECK-LABEL: LdOffset_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #2024, lsl #12 // =8290304
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; CHECK-NEXT: ldr x0, [x8, #29632]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i64, ptr %a, i64 1039992
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%val = load i64, ptr %arrayidx, align 4
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ret i64 %val
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}
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; LDRDroX
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define <2 x i32> @LdOffset_v2i32(ptr %a) {
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; CHECK-LABEL: LdOffset_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #2024, lsl #12 // =8290304
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; CHECK-NEXT: ldr d0, [x8, #29632]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds <2 x i32>, ptr %a, i64 1039992
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%val = load <2 x i32>, ptr %arrayidx, align 4
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ret <2 x i32> %val
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}
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; LDRQroX
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define <2 x i64> @LdOffset_v2i64(ptr %a) {
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; CHECK-LABEL: LdOffset_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #4048, lsl #12 // =16580608
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; CHECK-NEXT: ldr q0, [x8, #59264]
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds <2 x i64>, ptr %a, i64 1039992
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%val = load <2 x i64>, ptr %arrayidx, align 4
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ret <2 x i64> %val
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}
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; LDRSBWroX
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define double @LdOffset_i8_f64(ptr %a) {
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; CHECK-LABEL: LdOffset_i8_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
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; CHECK-NEXT: ldrsb w8, [x8, #3704]
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; CHECK-NEXT: scvtf d0, w8
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; CHECK-NEXT: ret
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%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
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%val = load i8, ptr %arrayidx, align 1
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%conv = sitofp i8 %val to double
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ret double %conv
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}
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; LDRSHWroX
|
|
define double @LdOffset_i16_f64(ptr %a) {
|
|
; CHECK-LABEL: LdOffset_i16_f64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
|
|
; CHECK-NEXT: ldrsh w8, [x8, #7408]
|
|
; CHECK-NEXT: scvtf d0, w8
|
|
; CHECK-NEXT: ret
|
|
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
|
|
%val = load i16, ptr %arrayidx, align 2
|
|
%conv = sitofp i16 %val to double
|
|
ret double %conv
|
|
}
|
|
|
|
; LDRSroX
|
|
define double @LdOffset_i32_f64(ptr %a) {
|
|
; CHECK-LABEL: LdOffset_i32_f64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
|
|
; CHECK-NEXT: ldr s0, [x8, #14816]
|
|
; CHECK-NEXT: ucvtf d0, d0
|
|
; CHECK-NEXT: ret
|
|
%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
|
|
%val = load i32, ptr %arrayidx, align 4
|
|
%conv = uitofp i32 %val to double
|
|
ret double %conv
|
|
}
|
|
|
|
; LDRDroX
|
|
define double @LdOffset_i64_f64(ptr %a) {
|
|
; CHECK-LABEL: LdOffset_i64_f64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: add x8, x0, #2024, lsl #12 // =8290304
|
|
; CHECK-NEXT: ldr d0, [x8, #29632]
|
|
; CHECK-NEXT: scvtf d0, d0
|
|
; CHECK-NEXT: ret
|
|
%arrayidx = getelementptr inbounds i64, ptr %a, i64 1039992
|
|
%val = load i64, ptr %arrayidx, align 8
|
|
%conv = sitofp i64 %val to double
|
|
ret double %conv
|
|
}
|
|
|
|
define i64 @LdOffset_i64_multi_offset(ptr %a) {
|
|
; CHECK-LABEL: LdOffset_i64_multi_offset:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: add x8, x0, #2031, lsl #12 // =8318976
|
|
; CHECK-NEXT: ldr x9, [x8, #960]
|
|
; CHECK-NEXT: ldr x8, [x8, #3016]
|
|
; CHECK-NEXT: add x0, x8, x9
|
|
; CHECK-NEXT: ret
|
|
%arrayidx = getelementptr inbounds i64, ptr %a, i64 1039992
|
|
%val0 = load i64, ptr %arrayidx, align 8
|
|
%arrayidx1 = getelementptr inbounds i64, ptr %a, i64 1040249
|
|
%val1 = load i64, ptr %arrayidx1, align 8
|
|
%add = add nsw i64 %val1, %val0
|
|
ret i64 %add
|
|
}
|
|
|
|
define i64 @LdOffset_i64_multi_offset_with_commmon_base(ptr %a) {
|
|
; CHECK-LABEL: LdOffset_i64_multi_offset_with_commmon_base:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: add x8, x0, #507, lsl #12 // =2076672
|
|
; CHECK-NEXT: ldr x9, [x8, #26464]
|
|
; CHECK-NEXT: ldr x8, [x8, #26496]
|
|
; CHECK-NEXT: add x0, x8, x9
|
|
; CHECK-NEXT: ret
|
|
%b = getelementptr inbounds i16, ptr %a, i64 1038336
|
|
%arrayidx = getelementptr inbounds i64, ptr %b, i64 3308
|
|
%val0 = load i64, ptr %arrayidx, align 8
|
|
%arrayidx1 = getelementptr inbounds i64, ptr %b, i64 3312
|
|
%val1 = load i64, ptr %arrayidx1, align 8
|
|
%add = add nsw i64 %val1, %val0
|
|
ret i64 %add
|
|
}
|
|
|
|
; Negative test: the offset is odd
|
|
define i32 @LdOffset_i16_odd_offset(ptr nocapture noundef readonly %a) {
|
|
; CHECK-LABEL: LdOffset_i16_odd_offset:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov w8, #56953 // =0xde79
|
|
; CHECK-NEXT: movk w8, #15, lsl #16
|
|
; CHECK-NEXT: ldrsh w0, [x0, x8]
|
|
; CHECK-NEXT: ret
|
|
%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039993
|
|
%val = load i16, ptr %arrayidx, align 2
|
|
%conv = sext i16 %val to i32
|
|
ret i32 %conv
|
|
}
|
|
|
|
; Already encoded with a single mov MOVNWi
|
|
define i8 @LdOffset_i8_movnwi(ptr %a) {
|
|
; CHECK-LABEL: LdOffset_i8_movnwi:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov w8, #16777215 // =0xffffff
|
|
; CHECK-NEXT: ldrb w0, [x0, x8]
|
|
; CHECK-NEXT: ret
|
|
%arrayidx = getelementptr inbounds i8, ptr %a, i64 16777215
|
|
%val = load i8, ptr %arrayidx, align 1
|
|
ret i8 %val
|
|
}
|
|
|
|
; Negative test: the offset is too large to encoded with a add
|
|
define i8 @LdOffset_i8_too_large(ptr %a) {
|
|
; CHECK-LABEL: LdOffset_i8_too_large:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov w8, #1 // =0x1
|
|
; CHECK-NEXT: movk w8, #256, lsl #16
|
|
; CHECK-NEXT: ldrb w0, [x0, x8]
|
|
; CHECK-NEXT: ret
|
|
%arrayidx = getelementptr inbounds i8, ptr %a, i64 16777217
|
|
%val = load i8, ptr %arrayidx, align 1
|
|
ret i8 %val
|
|
}
|