llvm-project/llvm/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll
Harvin Iriawan db158c7c83 [AArch64] Update generic sched model to A510
Refresh of the generic scheduling model to use A510 instead of A55.
  Main benefits are to the little core, and introducing SVE scheduling information.
  Changes tested on various OoO cores, no performance degradation is seen.

  Differential Revision: https://reviews.llvm.org/D156799
2023-08-21 12:25:15 +01:00

55 lines
1.8 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm64-apple-ios -mattr=+strict-align < %s | FileCheck %s
; Small (16 bytes here) unaligned memcpy() should be a function call if
; strict-alignment is turned on.
define void @t0(ptr %out, ptr %in) {
; CHECK-LABEL: t0:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: mov w2, #16 ; =0x10
; CHECK-NEXT: bl _memcpy
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: ret
entry:
call void @llvm.memcpy.p0.p0.i64(ptr %out, ptr %in, i64 16, i1 false)
ret void
}
; Small (16 bytes here) aligned memcpy() should be inlined even if
; strict-alignment is turned on.
define void @t1(ptr align 8 %out, ptr align 8 %in) {
; CHECK-LABEL: t1:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: ldp x9, x8, [x1]
; CHECK-NEXT: stp x9, x8, [x0]
; CHECK-NEXT: ret
entry:
call void @llvm.memcpy.p0.p0.i64(ptr align 8 %out, ptr align 8 %in, i64 16, i1 false)
ret void
}
; Tiny (4 bytes here) unaligned memcpy() should be inlined with byte sized
; loads and stores if strict-alignment is turned on.
define void @t2(ptr %out, ptr %in) {
; CHECK-LABEL: t2:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: ldrb w8, [x1, #3]
; CHECK-NEXT: ldrb w9, [x1, #2]
; CHECK-NEXT: ldrb w10, [x1]
; CHECK-NEXT: ldrb w11, [x1, #1]
; CHECK-NEXT: strb w8, [x0, #3]
; CHECK-NEXT: strb w9, [x0, #2]
; CHECK-NEXT: strb w11, [x0, #1]
; CHECK-NEXT: strb w10, [x0]
; CHECK-NEXT: ret
entry:
call void @llvm.memcpy.p0.p0.i64(ptr %out, ptr %in, i64 4, i1 false)
ret void
}
declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1)