61510b51c3
This reverts commit 9c319d5bb40785c969d2af76535ca62448dfafa7. Some issues were discovered with the bootstrap builds, which seem like they were caused by this commit. I'm reverting to investigate.
211 lines
5.3 KiB
LLVM
211 lines
5.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc < %s -mtriple=arm64-eabi -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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; rdar://9296808
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; rdar://9349137
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define i128 @t1(i64 %a, i64 %b) nounwind readnone ssp {
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; CHECK-LABEL: t1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mul x8, x0, x1
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; CHECK-NEXT: umulh x1, x0, x1
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; CHECK-NEXT: mov x0, x8
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; CHECK-NEXT: ret
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entry:
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%tmp1 = zext i64 %a to i128
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%tmp2 = zext i64 %b to i128
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%tmp3 = mul i128 %tmp1, %tmp2
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ret i128 %tmp3
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}
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define i128 @t2(i64 %a, i64 %b) nounwind readnone ssp {
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; CHECK-SD-LABEL: t2:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: mul x8, x0, x1
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; CHECK-SD-NEXT: smulh x1, x0, x1
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; CHECK-SD-NEXT: mov x0, x8
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: t2:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: asr x9, x1, #63
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; CHECK-GI-NEXT: asr x10, x0, #63
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; CHECK-GI-NEXT: mul x8, x0, x1
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; CHECK-GI-NEXT: mul x9, x0, x9
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; CHECK-GI-NEXT: umulh x11, x0, x1
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; CHECK-GI-NEXT: mov x0, x8
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; CHECK-GI-NEXT: madd x9, x10, x1, x9
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; CHECK-GI-NEXT: add x1, x9, x11
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; CHECK-GI-NEXT: ret
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entry:
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%tmp1 = sext i64 %a to i128
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%tmp2 = sext i64 %b to i128
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%tmp3 = mul i128 %tmp1, %tmp2
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ret i128 %tmp3
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}
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define i64 @t3(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: t3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: umull x0, w0, w1
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; CHECK-NEXT: ret
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entry:
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%tmp1 = zext i32 %a to i64
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%tmp2 = zext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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ret i64 %tmp3
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}
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define i64 @t4(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: t4:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: smull x0, w0, w1
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; CHECK-NEXT: ret
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entry:
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%tmp1 = sext i32 %a to i64
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%tmp2 = sext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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ret i64 %tmp3
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}
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define i64 @t5(i32 %a, i32 %b, i64 %c) nounwind {
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; CHECK-LABEL: t5:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: umaddl x0, w0, w1, x2
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; CHECK-NEXT: ret
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entry:
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%tmp1 = zext i32 %a to i64
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%tmp2 = zext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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%tmp4 = add i64 %c, %tmp3
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ret i64 %tmp4
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}
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define i64 @t6(i32 %a, i32 %b, i64 %c) nounwind {
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; CHECK-LABEL: t6:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: smsubl x0, w0, w1, x2
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; CHECK-NEXT: ret
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entry:
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%tmp1 = sext i32 %a to i64
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%tmp2 = sext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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%tmp4 = sub i64 %c, %tmp3
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ret i64 %tmp4
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}
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define i64 @t7(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: t7:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: umnegl x0, w0, w1
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; CHECK-NEXT: ret
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entry:
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%tmp1 = zext i32 %a to i64
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%tmp2 = zext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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%tmp4 = sub i64 0, %tmp3
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ret i64 %tmp4
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}
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define i64 @t8(i32 %a, i32 %b) nounwind {
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; CHECK-LABEL: t8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: smnegl x0, w0, w1
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; CHECK-NEXT: ret
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entry:
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%tmp1 = sext i32 %a to i64
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%tmp2 = sext i32 %b to i64
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%tmp3 = mul i64 %tmp1, %tmp2
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%tmp4 = sub i64 0, %tmp3
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ret i64 %tmp4
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}
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define i64 @t9(i32 %a) nounwind {
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; CHECK-LABEL: t9:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #8896 // =0x22c0
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; CHECK-NEXT: movk w8, #2, lsl #16
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; CHECK-NEXT: umull x0, w0, w8
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; CHECK-NEXT: ret
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entry:
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%tmp1 = zext i32 %a to i64
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%tmp2 = mul i64 %tmp1, 139968
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ret i64 %tmp2
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}
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; Check 64-bit multiplication is used for constants > 32 bits.
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define i64 @t10(i32 %a) nounwind {
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; CHECK-LABEL: t10:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: sxtw x8, w0
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; CHECK-NEXT: mov w9, #2 // =0x2
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; CHECK-NEXT: movk w9, #32768, lsl #16
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; CHECK-NEXT: mul x0, x8, x9
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; CHECK-NEXT: ret
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entry:
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%tmp1 = sext i32 %a to i64
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%tmp2 = mul i64 %tmp1, 2147483650 ; = 2^31 + 2
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ret i64 %tmp2
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}
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; Check the sext_inreg case.
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define i64 @t11(i64 %a) nounwind {
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; CHECK-LABEL: t11:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #29594 // =0x739a
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; CHECK-NEXT: movk w8, #65499, lsl #16
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; CHECK-NEXT: smnegl x0, w0, w8
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; CHECK-NEXT: ret
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entry:
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%tmp1 = trunc i64 %a to i32
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%tmp2 = sext i32 %tmp1 to i64
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%tmp3 = mul i64 %tmp2, -2395238
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%tmp4 = sub i64 0, %tmp3
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ret i64 %tmp4
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}
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define i64 @t12(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: t12:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #35118 // =0x892e
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; CHECK-NEXT: movk w8, #65008, lsl #16
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; CHECK-NEXT: smaddl x0, w0, w8, x1
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; CHECK-NEXT: ret
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entry:
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%tmp1 = trunc i64 %a to i32
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%tmp2 = sext i32 %tmp1 to i64
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%tmp3 = mul i64 %tmp2, -34567890
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%tmp4 = add i64 %b, %tmp3
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ret i64 %tmp4
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}
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define i64 @t13(i32 %a, i64 %b) nounwind {
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; CHECK-LABEL: t13:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #24910 // =0x614e
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; CHECK-NEXT: movk w8, #188, lsl #16
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; CHECK-NEXT: umsubl x0, w0, w8, x1
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; CHECK-NEXT: ret
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entry:
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%tmp1 = zext i32 %a to i64
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%tmp3 = mul i64 %tmp1, 12345678
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%tmp4 = sub i64 %b, %tmp3
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ret i64 %tmp4
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}
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define i64 @t14(i32 %a, i64 %b) nounwind {
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; CHECK-LABEL: t14:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #40626 // =0x9eb2
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; CHECK-NEXT: movk w8, #65347, lsl #16
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; CHECK-NEXT: smsubl x0, w0, w8, x1
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; CHECK-NEXT: ret
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entry:
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%tmp1 = sext i32 %a to i64
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%tmp3 = mul i64 %tmp1, -12345678
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%tmp4 = sub i64 %b, %tmp3
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ret i64 %tmp4
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}
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