db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
57 lines
2.0 KiB
LLVM
57 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm64-apple-ios | FileCheck %s
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define <4 x float> @foo(<4 x float> %val, <4 x float> %test) nounwind {
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; CHECK-LABEL: foo:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: fmov.4s v2, #1.00000000
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; CHECK-NEXT: fcmeq.4s v0, v0, v1
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; CHECK-NEXT: and.16b v0, v0, v2
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; CHECK-NEXT: ret
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%cmp = fcmp oeq <4 x float> %val, %test
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%ext = zext <4 x i1> %cmp to <4 x i32>
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%result = sitofp <4 x i32> %ext to <4 x float>
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ret <4 x float> %result
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}
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; Make sure the operation doesn't try to get folded when the sizes don't match,
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; as that ends up crashing later when trying to form a bitcast operation for
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; the folded nodes.
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define void @foo1(<4 x float> %val, <4 x float> %test, ptr %p) nounwind {
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; CHECK-LABEL: foo1:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: movi.4s v2, #1
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; CHECK-NEXT: fcmeq.4s v0, v0, v1
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; CHECK-NEXT: and.16b v0, v0, v2
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; CHECK-NEXT: ushll2.2d v1, v0, #0
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; CHECK-NEXT: ushll.2d v0, v0, #0
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; CHECK-NEXT: scvtf.2d v1, v1
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; CHECK-NEXT: scvtf.2d v0, v0
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; CHECK-NEXT: stp q0, q1, [x0]
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; CHECK-NEXT: ret
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%cmp = fcmp oeq <4 x float> %val, %test
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%ext = zext <4 x i1> %cmp to <4 x i32>
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%result = sitofp <4 x i32> %ext to <4 x double>
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store <4 x double> %result, ptr %p
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ret void
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}
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; Fold explicit AND operations when the constant isn't a splat of a single
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; scalar value like what the zext creates.
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define <4 x float> @foo2(<4 x float> %val, <4 x float> %test) nounwind {
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; CHECK-LABEL: foo2:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: fcmeq.4s v0, v0, v1
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; CHECK-NEXT: Lloh0:
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; CHECK-NEXT: adrp x8, lCPI2_0@PAGE
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; CHECK-NEXT: Lloh1:
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; CHECK-NEXT: ldr q1, [x8, lCPI2_0@PAGEOFF]
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; CHECK-NEXT: and.16b v0, v0, v1
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; CHECK-NEXT: ret
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; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1
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%cmp = fcmp oeq <4 x float> %val, %test
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%ext = zext <4 x i1> %cmp to <4 x i32>
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%and = and <4 x i32> %ext, <i32 255, i32 256, i32 257, i32 258>
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%result = sitofp <4 x i32> %and to <4 x float>
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ret <4 x float> %result
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}
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