3a51896ce8
Add basic handling for v1i64 saddsat, ssubsat, uaddsat and usubsat. We missed that these were not upgrading in #140454 due to a lack of test coverage, and for some reason the generic v1i64 nodes were not being treated as legal like they should. Fixes #142323
517 lines
17 KiB
LLVM
517 lines
17 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
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define <8 x i8> @sqadd8b(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: sqadd8b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: sqadd.8b v0, v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <8 x i8>, ptr %A
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%tmp2 = load <8 x i8>, ptr %B
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%tmp3 = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @sqadd4h(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: sqadd4h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: sqadd.4h v0, v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <4 x i16>, ptr %A
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%tmp2 = load <4 x i16>, ptr %B
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%tmp3 = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @sqadd2s(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: sqadd2s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: sqadd.2s v0, v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <2 x i32>, ptr %A
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%tmp2 = load <2 x i32>, ptr %B
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%tmp3 = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @sqadd1d(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: sqadd1d:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: sqadd d0, d0, d1
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; CHECK-NEXT: ret
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%tmp1 = load <1 x i64>, ptr %A
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%tmp2 = load <1 x i64>, ptr %B
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%tmp3 = call <1 x i64> @llvm.aarch64.neon.sqadd.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
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ret <1 x i64> %tmp3
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}
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define <8 x i8> @uqadd8b(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: uqadd8b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: uqadd.8b v0, v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <8 x i8>, ptr %A
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%tmp2 = load <8 x i8>, ptr %B
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%tmp3 = call <8 x i8> @llvm.aarch64.neon.uqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @uqadd4h(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: uqadd4h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: uqadd.4h v0, v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <4 x i16>, ptr %A
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%tmp2 = load <4 x i16>, ptr %B
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%tmp3 = call <4 x i16> @llvm.aarch64.neon.uqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @uqadd2s(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: uqadd2s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: uqadd.2s v0, v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <2 x i32>, ptr %A
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%tmp2 = load <2 x i32>, ptr %B
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%tmp3 = call <2 x i32> @llvm.aarch64.neon.uqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @uqadd1d(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: uqadd1d:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: uqadd d0, d0, d1
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; CHECK-NEXT: ret
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%tmp1 = load <1 x i64>, ptr %A
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%tmp2 = load <1 x i64>, ptr %B
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%tmp3 = call <1 x i64> @llvm.aarch64.neon.uqadd.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
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ret <1 x i64> %tmp3
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}
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define <16 x i8> @sqadd16b(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: sqadd16b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: sqadd.16b v0, v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <16 x i8>, ptr %A
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%tmp2 = load <16 x i8>, ptr %B
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%tmp3 = call <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @sqadd8h(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: sqadd8h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: sqadd.8h v0, v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <8 x i16>, ptr %A
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%tmp2 = load <8 x i16>, ptr %B
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%tmp3 = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @sqadd4s(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: sqadd4s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: sqadd.4s v0, v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <4 x i32>, ptr %A
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%tmp2 = load <4 x i32>, ptr %B
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @sqadd2d(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: sqadd2d:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: sqadd.2d v0, v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <2 x i64>, ptr %A
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%tmp2 = load <2 x i64>, ptr %B
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%tmp3 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i64> %tmp3
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}
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define <16 x i8> @uqadd16b(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: uqadd16b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: uqadd.16b v0, v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <16 x i8>, ptr %A
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%tmp2 = load <16 x i8>, ptr %B
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%tmp3 = call <16 x i8> @llvm.aarch64.neon.uqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @uqadd8h(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: uqadd8h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: uqadd.8h v0, v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <8 x i16>, ptr %A
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%tmp2 = load <8 x i16>, ptr %B
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%tmp3 = call <8 x i16> @llvm.aarch64.neon.uqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @uqadd4s(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: uqadd4s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: uqadd.4s v0, v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <4 x i32>, ptr %A
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%tmp2 = load <4 x i32>, ptr %B
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.uqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @uqadd2d(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: uqadd2d:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: uqadd.2d v0, v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <2 x i64>, ptr %A
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%tmp2 = load <2 x i64>, ptr %B
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%tmp3 = call <2 x i64> @llvm.aarch64.neon.uqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i64> %tmp3
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}
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declare <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare <1 x i64> @llvm.aarch64.neon.sqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
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declare <8 x i8> @llvm.aarch64.neon.uqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.aarch64.neon.uqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.aarch64.neon.uqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare <1 x i64> @llvm.aarch64.neon.uqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
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declare <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.aarch64.neon.uqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.aarch64.neon.uqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.aarch64.neon.uqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.aarch64.neon.uqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
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define <8 x i8> @usqadd8b(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: usqadd8b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: usqadd.8b v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <8 x i8>, ptr %A
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%tmp2 = load <8 x i8>, ptr %B
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%tmp3 = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @usqadd4h(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: usqadd4h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: usqadd.4h v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <4 x i16>, ptr %A
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%tmp2 = load <4 x i16>, ptr %B
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%tmp3 = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @usqadd2s(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: usqadd2s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: usqadd.2s v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <2 x i32>, ptr %A
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%tmp2 = load <2 x i32>, ptr %B
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%tmp3 = call <2 x i32> @llvm.aarch64.neon.usqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @usqadd1d(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: usqadd1d:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr d0, [x0]
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; CHECK-NEXT: ldr d1, [x1]
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; CHECK-NEXT: usqadd d0, d1
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; CHECK-NEXT: ret
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%tmp1 = load <1 x i64>, ptr %A
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%tmp2 = load <1 x i64>, ptr %B
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%tmp3 = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
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ret <1 x i64> %tmp3
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}
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define <16 x i8> @usqadd16b(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: usqadd16b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: usqadd.16b v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <16 x i8>, ptr %A
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%tmp2 = load <16 x i8>, ptr %B
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%tmp3 = call <16 x i8> @llvm.aarch64.neon.usqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @usqadd8h(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: usqadd8h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: usqadd.8h v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <8 x i16>, ptr %A
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%tmp2 = load <8 x i16>, ptr %B
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%tmp3 = call <8 x i16> @llvm.aarch64.neon.usqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @usqadd4s(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: usqadd4s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: usqadd.4s v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <4 x i32>, ptr %A
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%tmp2 = load <4 x i32>, ptr %B
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.usqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @usqadd2d(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: usqadd2d:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: usqadd.2d v0, v1
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; CHECK-NEXT: ret
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%tmp1 = load <2 x i64>, ptr %A
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%tmp2 = load <2 x i64>, ptr %B
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%tmp3 = call <2 x i64> @llvm.aarch64.neon.usqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i64> %tmp3
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}
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define i64 @usqadd_d(i64 %l, i64 %r) nounwind {
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; CHECK-LABEL: usqadd_d:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov d0, x0
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; CHECK-NEXT: fmov d1, x1
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; CHECK-NEXT: usqadd d0, d1
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; CHECK-NEXT: fmov x0, d0
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; CHECK-NEXT: ret
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%sum = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %l, i64 %r)
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ret i64 %sum
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}
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define i32 @usqadd_s(i32 %l, i32 %r) nounwind {
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; CHECK-LABEL: usqadd_s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s0, w0
|
|
; CHECK-NEXT: fmov s1, w1
|
|
; CHECK-NEXT: usqadd s0, s1
|
|
; CHECK-NEXT: fmov w0, s0
|
|
; CHECK-NEXT: ret
|
|
%sum = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %l, i32 %r)
|
|
ret i32 %sum
|
|
}
|
|
|
|
declare <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
|
|
declare <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
|
|
declare <2 x i32> @llvm.aarch64.neon.usqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
|
|
declare <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
|
|
declare i64 @llvm.aarch64.neon.usqadd.i64(i64, i64) nounwind readnone
|
|
declare i32 @llvm.aarch64.neon.usqadd.i32(i32, i32) nounwind readnone
|
|
|
|
declare <16 x i8> @llvm.aarch64.neon.usqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
|
|
declare <8 x i16> @llvm.aarch64.neon.usqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
|
|
declare <4 x i32> @llvm.aarch64.neon.usqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
|
|
declare <2 x i64> @llvm.aarch64.neon.usqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
|
|
|
|
|
|
define <8 x i8> @suqadd8b(ptr %A, ptr %B) nounwind {
|
|
; CHECK-LABEL: suqadd8b:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr d0, [x0]
|
|
; CHECK-NEXT: ldr d1, [x1]
|
|
; CHECK-NEXT: suqadd.8b v0, v1
|
|
; CHECK-NEXT: ret
|
|
%tmp1 = load <8 x i8>, ptr %A
|
|
%tmp2 = load <8 x i8>, ptr %B
|
|
%tmp3 = call <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
|
|
ret <8 x i8> %tmp3
|
|
}
|
|
|
|
define <4 x i16> @suqadd4h(ptr %A, ptr %B) nounwind {
|
|
; CHECK-LABEL: suqadd4h:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr d0, [x0]
|
|
; CHECK-NEXT: ldr d1, [x1]
|
|
; CHECK-NEXT: suqadd.4h v0, v1
|
|
; CHECK-NEXT: ret
|
|
%tmp1 = load <4 x i16>, ptr %A
|
|
%tmp2 = load <4 x i16>, ptr %B
|
|
%tmp3 = call <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
|
|
ret <4 x i16> %tmp3
|
|
}
|
|
|
|
define <2 x i32> @suqadd2s(ptr %A, ptr %B) nounwind {
|
|
; CHECK-LABEL: suqadd2s:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr d0, [x0]
|
|
; CHECK-NEXT: ldr d1, [x1]
|
|
; CHECK-NEXT: suqadd.2s v0, v1
|
|
; CHECK-NEXT: ret
|
|
%tmp1 = load <2 x i32>, ptr %A
|
|
%tmp2 = load <2 x i32>, ptr %B
|
|
%tmp3 = call <2 x i32> @llvm.aarch64.neon.suqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
|
|
ret <2 x i32> %tmp3
|
|
}
|
|
|
|
define <1 x i64> @suqadd1d(ptr %A, ptr %B) nounwind {
|
|
; CHECK-LABEL: suqadd1d:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr d0, [x0]
|
|
; CHECK-NEXT: ldr d1, [x1]
|
|
; CHECK-NEXT: suqadd d0, d1
|
|
; CHECK-NEXT: ret
|
|
%tmp1 = load <1 x i64>, ptr %A
|
|
%tmp2 = load <1 x i64>, ptr %B
|
|
%tmp3 = call <1 x i64> @llvm.aarch64.neon.suqadd.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
|
|
ret <1 x i64> %tmp3
|
|
}
|
|
|
|
|
|
define <16 x i8> @suqadd16b(ptr %A, ptr %B) nounwind {
|
|
; CHECK-LABEL: suqadd16b:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: ldr q1, [x1]
|
|
; CHECK-NEXT: suqadd.16b v0, v1
|
|
; CHECK-NEXT: ret
|
|
%tmp1 = load <16 x i8>, ptr %A
|
|
%tmp2 = load <16 x i8>, ptr %B
|
|
%tmp3 = call <16 x i8> @llvm.aarch64.neon.suqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
|
|
ret <16 x i8> %tmp3
|
|
}
|
|
|
|
define <8 x i16> @suqadd8h(ptr %A, ptr %B) nounwind {
|
|
; CHECK-LABEL: suqadd8h:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: ldr q1, [x1]
|
|
; CHECK-NEXT: suqadd.8h v0, v1
|
|
; CHECK-NEXT: ret
|
|
%tmp1 = load <8 x i16>, ptr %A
|
|
%tmp2 = load <8 x i16>, ptr %B
|
|
%tmp3 = call <8 x i16> @llvm.aarch64.neon.suqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
|
|
ret <8 x i16> %tmp3
|
|
}
|
|
|
|
define <4 x i32> @suqadd4s(ptr %A, ptr %B) nounwind {
|
|
; CHECK-LABEL: suqadd4s:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: ldr q1, [x1]
|
|
; CHECK-NEXT: suqadd.4s v0, v1
|
|
; CHECK-NEXT: ret
|
|
%tmp1 = load <4 x i32>, ptr %A
|
|
%tmp2 = load <4 x i32>, ptr %B
|
|
%tmp3 = call <4 x i32> @llvm.aarch64.neon.suqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
|
|
ret <4 x i32> %tmp3
|
|
}
|
|
|
|
define <2 x i64> @suqadd2d(ptr %A, ptr %B) nounwind {
|
|
; CHECK-LABEL: suqadd2d:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldr q0, [x0]
|
|
; CHECK-NEXT: ldr q1, [x1]
|
|
; CHECK-NEXT: suqadd.2d v0, v1
|
|
; CHECK-NEXT: ret
|
|
%tmp1 = load <2 x i64>, ptr %A
|
|
%tmp2 = load <2 x i64>, ptr %B
|
|
%tmp3 = call <2 x i64> @llvm.aarch64.neon.suqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
|
|
ret <2 x i64> %tmp3
|
|
}
|
|
|
|
define i64 @suqadd_d(i64 %l, i64 %r) nounwind {
|
|
; CHECK-LABEL: suqadd_d:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: fmov d0, x0
|
|
; CHECK-NEXT: fmov d1, x1
|
|
; CHECK-NEXT: suqadd d0, d1
|
|
; CHECK-NEXT: fmov x0, d0
|
|
; CHECK-NEXT: ret
|
|
%sum = call i64 @llvm.aarch64.neon.suqadd.i64(i64 %l, i64 %r)
|
|
ret i64 %sum
|
|
}
|
|
|
|
define i32 @suqadd_s(i32 %l, i32 %r) nounwind {
|
|
; CHECK-LABEL: suqadd_s:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: fmov s0, w0
|
|
; CHECK-NEXT: fmov s1, w1
|
|
; CHECK-NEXT: suqadd s0, s1
|
|
; CHECK-NEXT: fmov w0, s0
|
|
; CHECK-NEXT: ret
|
|
%sum = call i32 @llvm.aarch64.neon.suqadd.i32(i32 %l, i32 %r)
|
|
ret i32 %sum
|
|
}
|
|
|
|
declare <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
|
|
declare <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
|
|
declare <2 x i32> @llvm.aarch64.neon.suqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
|
|
declare <1 x i64> @llvm.aarch64.neon.suqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
|
|
declare i64 @llvm.aarch64.neon.suqadd.i64(i64, i64) nounwind readnone
|
|
declare i32 @llvm.aarch64.neon.suqadd.i32(i32, i32) nounwind readnone
|
|
|
|
declare <16 x i8> @llvm.aarch64.neon.suqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
|
|
declare <8 x i16> @llvm.aarch64.neon.suqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
|
|
declare <4 x i32> @llvm.aarch64.neon.suqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
|
|
declare <2 x i64> @llvm.aarch64.neon.suqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
|