61510b51c3
This reverts commit 9c319d5bb40785c969d2af76535ca62448dfafa7. Some issues were discovered with the bootstrap builds, which seem like they were caused by this commit. I'm reverting to investigate.
263 lines
7.4 KiB
LLVM
263 lines
7.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s | FileCheck %s
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target triple = "aarch64"
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; First some corner cases
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define <4 x float> @f_v4_s0(<4 x i32> %u) {
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; CHECK-LABEL: f_v4_s0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: scvtf v0.4s, v0.4s
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; CHECK-NEXT: ret
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%s = ashr exact <4 x i32> %u, <i32 0, i32 0, i32 0, i32 0>
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%v = sitofp <4 x i32> %s to <4 x float>
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ret <4 x float> %v
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}
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define <4 x float> @f_v4_s1(<4 x i32> %u) {
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; CHECK-LABEL: f_v4_s1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: scvtf v0.4s, v0.4s, #1
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; CHECK-NEXT: ret
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%s = ashr exact <4 x i32> %u, <i32 1, i32 1, i32 1, i32 1>
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%v = sitofp <4 x i32> %s to <4 x float>
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ret <4 x float> %v
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}
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define <4 x float> @f_v4_s24_inexact(<4 x i32> %u) {
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; CHECK-LABEL: f_v4_s24_inexact:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshr v0.4s, v0.4s, #24
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; CHECK-NEXT: scvtf v0.4s, v0.4s
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; CHECK-NEXT: ret
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%s = ashr <4 x i32> %u, <i32 24, i32 24, i32 24, i32 24>
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%v = sitofp <4 x i32> %s to <4 x float>
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ret <4 x float> %v
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}
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define <4 x float> @f_v4_s31(<4 x i32> %u) {
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; CHECK-LABEL: f_v4_s31:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-NEXT: scvtf v0.4s, v0.4s
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; CHECK-NEXT: ret
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%s = ashr <4 x i32> %u, <i32 31, i32 31, i32 31, i32 31>
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%v = sitofp <4 x i32> %s to <4 x float>
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ret <4 x float> %v
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}
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; Common cases for conversion from signed integer to floating point types
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define <2 x float> @f_v2_s24(<2 x i32> %u) {
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; CHECK-LABEL: f_v2_s24:
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; CHECK: // %bb.0:
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; CHECK-NEXT: scvtf v0.2s, v0.2s, #24
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; CHECK-NEXT: ret
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%s = ashr exact <2 x i32> %u, <i32 24, i32 24>
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%v = sitofp <2 x i32> %s to <2 x float>
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ret <2 x float> %v
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}
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define <4 x float> @f_v4_s24(<4 x i32> %u) {
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; CHECK-LABEL: f_v4_s24:
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; CHECK: // %bb.0:
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; CHECK-NEXT: scvtf v0.4s, v0.4s, #24
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; CHECK-NEXT: ret
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%s = ashr exact <4 x i32> %u, <i32 24, i32 24, i32 24, i32 24>
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%v = sitofp <4 x i32> %s to <4 x float>
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ret <4 x float> %v
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}
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; Check legalisation to <2 x f64> does not get in the way
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define <8 x double> @d_v8_s64(<8 x i64> %u) {
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; CHECK-LABEL: d_v8_s64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: scvtf v0.2d, v0.2d, #56
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; CHECK-NEXT: scvtf v1.2d, v1.2d, #56
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; CHECK-NEXT: scvtf v2.2d, v2.2d, #56
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; CHECK-NEXT: scvtf v3.2d, v3.2d, #56
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; CHECK-NEXT: ret
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%s = ashr exact <8 x i64> %u, <i64 56, i64 56, i64 56, i64 56, i64 56, i64 56, i64 56, i64 56>
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%v = sitofp <8 x i64> %s to <8 x double>
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ret <8 x double> %v
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}
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define <4 x half> @h_v4_s8(<4 x i16> %u) #0 {
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; CHECK-LABEL: h_v4_s8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: scvtf v0.4h, v0.4h, #8
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; CHECK-NEXT: ret
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%s = ashr exact <4 x i16> %u, <i16 8, i16 8, i16 8, i16 8>
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%v = sitofp <4 x i16> %s to <4 x half>
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ret <4 x half> %v
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}
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define <8 x half> @h_v8_s8(<8 x i16> %u) #0 {
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; CHECK-LABEL: h_v8_s8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: scvtf v0.8h, v0.8h, #8
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; CHECK-NEXT: ret
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%s = ashr exact <8 x i16> %u, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%v = sitofp <8 x i16> %s to <8 x half>
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ret <8 x half> %v
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}
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; int-to-fp conversion of element in lane 0 should apply
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; cvtf on vector subregister to avoid fpr->gpr trip
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define float @l0_extract_f_v2s(<2 x i32> %u) {
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; CHECK-LABEL: l0_extract_f_v2s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: scvtf s0, s0
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; CHECK-NEXT: ret
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%i = extractelement <2 x i32> %u, i64 0
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%f = sitofp i32 %i to float
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ret float %f
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}
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; cvtf to use ssub for bottom 32-bits from v2i32
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define float @l0_extract_f_v2u(<2 x i32> %u) {
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; CHECK-LABEL: l0_extract_f_v2u:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: ucvtf s0, s0
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; CHECK-NEXT: ret
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%i = extractelement <2 x i32> %u, i64 0
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%f = uitofp i32 %i to float
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ret float %f
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}
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; Pattern should only apply when it is known to be lane 0
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define float @ln_extract_f_v2s(<2 x i32> %u, i64 %n) {
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; CHECK-LABEL: ln_extract_f_v2s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: add x8, sp, #8
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; CHECK-NEXT: str d0, [sp, #8]
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; CHECK-NEXT: bfi x8, x0, #2, #1
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; CHECK-NEXT: ldr s0, [x8]
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; CHECK-NEXT: scvtf s0, s0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%i = extractelement <2 x i32> %u, i64 %n
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%f = sitofp i32 %i to float
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ret float %f
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}
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; cvtf to use ssub for bottom 32-bits from v4i32
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define float @l0_extract_f_v4s(<4 x i32> %u) {
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; CHECK-LABEL: l0_extract_f_v4s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: scvtf s0, s0
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; CHECK-NEXT: ret
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%i = extractelement <4 x i32> %u, i64 0
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%f = sitofp i32 %i to float
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ret float %f
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}
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define float @l0_extract_f_v4u(<4 x i32> %u) {
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; CHECK-LABEL: l0_extract_f_v4u:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ucvtf s0, s0
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; CHECK-NEXT: ret
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%i = extractelement <4 x i32> %u, i64 0
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%f = uitofp i32 %i to float
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ret float %f
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}
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define float @ln_extract_f_v4s(<4 x i32> %u, i64 %n) {
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; CHECK-LABEL: ln_extract_f_v4s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: mov x8, sp
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; CHECK-NEXT: str q0, [sp]
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; CHECK-NEXT: bfi x8, x0, #2, #2
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; CHECK-NEXT: ldr s0, [x8]
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; CHECK-NEXT: scvtf s0, s0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%i = extractelement <4 x i32> %u, i64 %n
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%f = sitofp i32 %i to float
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ret float %f
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}
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; cvtf to use dsub for bottom 64-bits from v2i64
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define double @l0_extract_d_v2s(<2 x i64> %u) {
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; CHECK-LABEL: l0_extract_d_v2s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: scvtf d0, d0
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; CHECK-NEXT: ret
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%i = extractelement <2 x i64> %u, i64 0
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%f = sitofp i64 %i to double
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ret double %f
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}
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define double @l0_extract_d_v2u(<2 x i64> %u) {
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; CHECK-LABEL: l0_extract_d_v2u:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ucvtf d0, d0
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; CHECK-NEXT: ret
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%i = extractelement <2 x i64> %u, i64 0
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%f = uitofp i64 %i to double
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ret double %f
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}
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define double @ln_extract_d_v2s(<2 x i64> %u, i64 %n) {
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; CHECK-LABEL: ln_extract_d_v2s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: mov x8, sp
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; CHECK-NEXT: str q0, [sp]
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; CHECK-NEXT: bfi x8, x0, #3, #1
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; CHECK-NEXT: ldr d0, [x8]
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; CHECK-NEXT: scvtf d0, d0
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%i = extractelement <2 x i64> %u, i64 %n
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%f = sitofp i64 %i to double
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ret double %f
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}
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; (fullfp16) cvtf to use hsub for bottom 16-bits from v8i16
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define half @l0_extract_h_v8s(<8 x i16> %u) #0 {
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; CHECK-LABEL: l0_extract_h_v8s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: scvtf h0, h0
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; CHECK-NEXT: ret
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%i = extractelement <8 x i16> %u, i32 0
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%f = sitofp i16 %i to half
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ret half %f
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}
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define half @l0_extract_h_v8u(<8 x i16> %u) #0 {
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; CHECK-LABEL: l0_extract_h_v8u:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ucvtf h0, h0
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; CHECK-NEXT: ret
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%i = extractelement <8 x i16> %u, i32 0
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%f = uitofp i16 %i to half
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ret half %f
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}
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define half @ln_extract_h_v8u(<8 x i16> %u, i32 %n) #0 {
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; CHECK-LABEL: ln_extract_h_v8u:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: mov x8, sp
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: str q0, [sp]
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; CHECK-NEXT: bfi x8, x0, #1, #3
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; CHECK-NEXT: ldrh w8, [x8]
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; CHECK-NEXT: ucvtf h0, w8
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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%i = extractelement <8 x i16> %u, i32 %n
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%f = uitofp i16 %i to half
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ret half %f
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}
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attributes #0 = { "target-features"="+fullfp16"}
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