de88371d9d
[LLVM][AArch64] Add ASM constraints for reduced GPR register ranges.
The patch adds the follow ASM constraints:
Uci => w8-w11/x8-x11
Ucj => w12-w15/x12-x15
These constraints are required for SME load/store instructions
where a reduced set of GPRs are used to specify ZA array vectors.
NOTE: GCC has agreed to use the same constraint syntax.
79 lines
2.2 KiB
LLVM
79 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc < %s -o - | FileCheck %s
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target triple = "arm64-none-linux-gnu"
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define void @test_constraints_Uci_w(i32 %a) {
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; CHECK-LABEL: test_constraints_Uci_w:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: //APP
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; CHECK-NEXT: add x0, x0, x8
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; CHECK-NEXT: //NO_APP
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; CHECK-NEXT: ret
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call void asm sideeffect "add x0, x0, $0", "@3Uci,~{x0}"(i32 %a)
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ret void
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}
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; As test_constraints_Uci_w but ensures non-legal types are also covered.
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define void @test_constraints_Uci_w_i8(i8 %a) {
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; CHECK-LABEL: test_constraints_Uci_w_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: //APP
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; CHECK-NEXT: add x0, x0, x8
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; CHECK-NEXT: //NO_APP
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; CHECK-NEXT: ret
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call void asm sideeffect "add x0, x0, $0", "@3Uci,~{x0}"(i8 %a)
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ret void
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}
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define void @test_constraints_Uci_x(i64 %a) {
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; CHECK-LABEL: test_constraints_Uci_x:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, x0
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; CHECK-NEXT: //APP
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; CHECK-NEXT: add x0, x0, x8
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; CHECK-NEXT: //NO_APP
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; CHECK-NEXT: ret
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call void asm sideeffect "add x0, x0, $0", "@3Uci,~{x0}"(i64 %a)
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ret void
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}
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define void @test_constraint_Ucj_w(i32 %a) {
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; CHECK-LABEL: test_constraint_Ucj_w:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w12, w0
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; CHECK-NEXT: //APP
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; CHECK-NEXT: add x0, x0, x12
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; CHECK-NEXT: //NO_APP
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; CHECK-NEXT: ret
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call void asm sideeffect "add x0, x0, $0", "@3Ucj,~{x0}"(i32 %a)
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ret void
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}
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; As test_constraints_Ucj_w but ensures non-legal types are also covered.
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define void @test_constraint_Ucj_w_i8(i8 %a) {
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; CHECK-LABEL: test_constraint_Ucj_w_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w12, w0
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; CHECK-NEXT: //APP
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; CHECK-NEXT: add x0, x0, x12
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; CHECK-NEXT: //NO_APP
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; CHECK-NEXT: ret
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call void asm sideeffect "add x0, x0, $0", "@3Ucj,~{x0}"(i8 %a)
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ret void
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}
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define void @test_constraint_Ucj_x(i64 %a) {
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; CHECK-LABEL: test_constraint_Ucj_x:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x12, x0
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; CHECK-NEXT: //APP
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; CHECK-NEXT: add x0, x0, x12
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; CHECK-NEXT: //NO_APP
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; CHECK-NEXT: ret
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call void asm sideeffect "add x0, x0, $0", "@3Ucj,~{x0}"(i64 %a)
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ret void
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}
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