David Green b0bfbad19b [AArch64] Always lower fp16 zero to FMOVH0
We can always use FMOVH0 to lower fp16 zero, even without fullfp16. We can
either expand it to movi d0, #0 or fmov s0, wzr, which will both clear all the
bits of the register.

Differential Revision: https://reviews.llvm.org/D143988
2023-02-15 16:06:32 +00:00

13 lines
449 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;; -mattr=+all is not intended to be used for code emitters. Nevertheless,
;; llc does not reject it. This test intends to catch behavior changes.
; RUN: llc -mtriple=aarch64 -mattr=+all < %s | FileCheck %s
define half @bf16() nounwind {
; CHECK-LABEL: bf16:
; CHECK: // %bb.0:
; CHECK-NEXT: movi d0, #0000000000000000
; CHECK-NEXT: ret
ret half 0xH0000
}