db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
94 lines
3.7 KiB
LLVM
94 lines
3.7 KiB
LLVM
; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=-fuse-adrp-add,-fuse-literals | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKDONT
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=+fuse-adrp-add,+fuse-literals | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a65 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m5 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE
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; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-n1 | FileCheck %s --check-prefix=CHECKFUSE-NEOVERSE
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@g = common local_unnamed_addr global ptr null, align 8
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define dso_local ptr @litp(i32 %a, i32 %b) {
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entry:
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%add = add nsw i32 %b, %a
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%idx.ext = sext i32 %add to i64
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%add.ptr = getelementptr i8, ptr @litp, i64 %idx.ext
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store ptr %add.ptr, ptr @g, align 8
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ret ptr %add.ptr
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; CHECK-LABEL: litp:
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; CHECK: adrp [[R:x[0-9]+]], litp
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; CHECKFUSE-NEXT: add {{x[0-9]+}}, [[R]], :lo12:litp
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}
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define dso_local ptr @litp_tune_generic(i32 %a, i32 %b) "tune-cpu"="generic" {
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entry:
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%add = add nsw i32 %b, %a
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%idx.ext = sext i32 %add to i64
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%add.ptr = getelementptr i8, ptr @litp_tune_generic, i64 %idx.ext
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store ptr %add.ptr, ptr @g, align 8
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ret ptr %add.ptr
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; CHECK-LABEL: litp_tune_generic:
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; CHECK: adrp [[R:x[0-9]+]], litp_tune_generic
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; CHECKDONT: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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; CHECK-NEXT: add {{x[0-9]+}}, [[R]], :lo12:litp_tune_generic
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}
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define dso_local ptr @litp_tune_neoverse_n1(i32 %a, i32 %b) "tune-cpu"="neoverse-n1" {
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entry:
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%add = add nsw i32 %b, %a
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%idx.ext = sext i32 %add to i64
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%add.ptr = getelementptr i8, ptr @litp_tune_generic, i64 %idx.ext
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store ptr %add.ptr, ptr @g, align 8
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ret ptr %add.ptr
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; CHECKFUSE-NEOVERSE-LABEL: litp_tune_neoverse_n1:
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; CHECKFUSE-NEOVERSE: adrp [[R:x[0-9]+]], litp_tune_generic
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; CHECKFUSE-NEOVERSE-NEXT: add {{x[0-9]+}}, [[R]], :lo12:litp_tune_generic
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}
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define dso_local i32 @liti(i32 %a, i32 %b) {
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entry:
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%add = add i32 %a, -262095121
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%add1 = add i32 %add, %b
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ret i32 %add1
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; CHECK-LABEL: liti:
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; CHECK: mov [[R:w[0-9]+]], {{#[0-9]+}}
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; CHECKDONT-NEXT: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
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; CHECKFUSE-NEXT: movk [[R]], {{#[0-9]+}}, lsl #16
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}
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; Function Attrs: norecurse nounwind readnone
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define dso_local i64 @litl(i64 %a, i64 %b) {
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entry:
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%add = add i64 %a, 2208998440489107183
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%add1 = add i64 %add, %b
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ret i64 %add1
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; CHECK-LABEL: litl:
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; CHECK: mov [[R:x[0-9]+]], {{#[0-9]+}}
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; CHECKDONT-NEXT: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
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; CHECK-NEXT: movk [[R]], {{#[0-9]+}}, lsl #16
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; CHECK: movk [[R]], {{#[0-9]+}}, lsl #32
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; CHECK-NEXT: movk [[R]], {{#[0-9]+}}, lsl #48
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}
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; Function Attrs: norecurse nounwind readnone
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define dso_local double @litf() {
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entry:
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ret double 0x400921FB54442D18
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; CHECK-LABEL: litf:
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; CHECK-DONT: adrp [[ADDR:x[0-9]+]], [[CSTLABEL:.LCP.*]]
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; CHECK-DONT-NEXT: ldr {{d[0-9]+}}, {{[[]}}[[ADDR]], :lo12:[[CSTLABEL]]{{[]]}}
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; CHECK-FUSE: mov [[R:x[0-9]+]], #11544
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; CHECK-FUSE: movk [[R]], #21572, lsl #16
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; CHECK-FUSE: movk [[R]], #8699, lsl #32
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; CHECK-FUSE: movk [[R]], #16393, lsl #48
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; CHECK-FUSE: fmov {{d[0-9]+}}, [[R]]
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}
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